Mesa (broadwell): 37 new commits

Thu Dec 12 09:37:50 UTC 2013

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ee1c49d3568e8f3cc55db4946d05854bbd59e67
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Dec 10 14:21:08 2013 -0800

    3DSTATE_CONSTANT_XS MOCS fixup
    
    MOCS doesn't go here

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=28b3df6e4b41efa772946bfa1b0f6e246bcf5699
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Nov 1 11:41:34 2013 -0700

    i965: Add Broadwell PCI IDs.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7943d8ceb77524f696258b2c7f6b07ca33456f23
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Dec 6 15:37:20 2013 -0800

    SF/VS URB read output fixes...?

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2641dd0c226ebd135f6096590c0530ea1a0b448
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Dec 6 03:07:54 2013 -0800

    i965: Disable 3DSTATE_WM_HZ_OP fields.
    
    We'll need to do better than this when we implement multisampling, HiZ,
    or fast clears...but for now, this will do.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebb995917b64a85672c125f6093512af4dcb2469
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Nov 18 10:10:07 2013 -0800

    i965: Fix MI_STORE_REGISTER_MEM for Broadwell.
    
    It now takes a 48-bit address.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9677d0b09c0b393cc387e682c66c50d4596d3c2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Nov 8 22:21:56 2013 -0800

    i965: Fix up PIPE_CONTROL packets for Broadwell?
    
    I believe these need to grow by 1 DWord for the AddressHigh bits.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a31f61c9fb5054515d63c94706a4d6482b39822
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Nov 8 22:21:29 2013 -0800

    i965: Disable workaround flush for push constants on Broadwell.
    
    If it wasn't necessary for Haswell, it's likely not to be necessary for
    Broadwell either.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eeaa6b41673caefd0887988967f1d3b8f7b52d5c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Nov 11 18:30:32 2013 -0800

    i965: Emit 3DSTATE_VF on Broadwell too.
    
    It's not just for Haswell.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=df4501d6ab9b2878c46236e9a474f4e07adcf81b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Nov 8 21:58:35 2013 -0800

    i965: Emit HIER_DEPTH_BUFFER too
    
    this depth buffer code is crap

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e8cd69e52acc9e33672f4a2bd744c6e982c8f49
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Nov 4 23:19:55 2013 -0800

    i965: Update GS state for Broadwell.
    
    This is quite similar to the Gen7 code.  The main changes:
     - 48-bit relocations
     - Thread count is specified as U/2-1 instead of U-1.
     - An extra DWord (DW9) with clip planes, URB entry output length/offsets
     - We need to program the "Expected Vertex Count" (VerticesIn)
    
    v2: Set the number of binding table entries so they can be prefetched
        (requested by Eric Anholt).
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f51f3acc6160fd41a171ed3524a7a9bc72a615a3
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Dec 3 15:20:37 2012 -0800

    i965: Update multisampling state for Broadwell.
    
    On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
    samples, pixel location, and the positions of each sample within a pixel
    for each multisampling mode (4x and 8x).  It was also a non-pipelined
    command, presumably since changing the sample positions is fairly
    drastic.
    
    Broadwell improves upon this by splitting the sample positions out into
    a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN.  With
    that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.
    
    Broadwell also supports 2x and 16x multisampling, in addition to the 4x
    and 8x supported by Gen7.  This patch, however, does not implement 2x
    and 16x.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
    Signed-off-by: Chad Versace <chad.versace at linux.intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=630a5462f476dcfd06e170650c25d174b385909a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Sat Jan 12 16:12:38 2013 -0800

    i965: Update blitter code for 48-bit addresses.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=295d09d766d8e67ac5a99f55298d378bf662ac47
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Dec 14 03:58:30 2012 -0800

    i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.
    
    (This patch was written before Paul's refactor to reuse
     brw_emit_depthbuffer and just implement a gen7_emit_depth_stencil_hiz
     function.  We should probably rearchitect it to fit that new model, as
     it's much better.  --Ken)
    
    (The rest of this commit message was written by Chad.)
    
    The depth buffer packet emitted by this patchis incomplete.
    
    We must use the packet's level/layer fields to specify the miptree slice
    into which to render. This patch emits 0 there, and hence all rendering
    occurs to the miptree's base slice. (In gen5 through gen7, we used the
    intra-tile x/y offsets to specify the miptree slice. But gen8 removed
    those fields.)
    
    However, the incomplete implementation does show some signs of life.  It
    fixes the page fault in piglit:fbo-depth. (The test's segfault was
    likely due to the high 16 bits of the surface base address being
    invalid).
    
    v2: [chadv]
      - Comment in patch that depth buffer packet needs level/layer
        fields.
      - Remove comments specific to gen7.
      - Expand commit message.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
    Signed-off-by: Chad Versace <chad.versace at linux.intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=948f4e92f41f99f58bf9044071999a94cd315a16
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Dec 5 19:30:26 2012 -0800

    i965: Update BLEND_STATE for Broadwell.
    
    v2: Allow logic ops on all surface types.  The UNORM restriction was
        lifted with Haswell and I simply hadn't noticed.  Also, add missing
        BRW_NEW_STATE_BASE_ADDRESS dirty bit.  Both caught by Eric Anholt.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9975c410648c570704fde590f51fb40b3c230cb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Dec 5 15:34:34 2012 -0800

    i965: Update SF_CLIP_VIEWPORT for Broadwell.
    
    It has more fields now.  Not sure if this is correct for render_to_fbo.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1876ef230b306beb5d8ce5878159333d82d6261
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Dec 4 16:39:03 2012 -0800

    i965: Rework SURFACE_STATE entries for Broadwell.
    
    v2: Add missing SCS setting in gen8_emit_buffer_surface_state (caught by
        Eric Anholt).
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5d8cd5b4a04c608ef4ddf08c827c378b165209c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Dec 4 14:45:19 2012 -0800

    i965: Update SOL state for Broadwell.
    
    Unlike on Gen7, we can directly set the offset via the state packet.
    We also -have- to: the kernel SOL reset code won't work anymore.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a43e49c6d89d85ad22a817bc5d1c95607ebcf740
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Nov 28 21:39:19 2012 -0800

    i965: Update the code that disables unused shader stages for Broadwell.
    
    v2: Also disable 3DSTATE_WM_CHROMAKEY for safety.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Eric Anholt <eric at anholt.net> [v1]

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=121fa489768b189c1f2654a1791efb5ec0806636
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Dec 4 11:39:14 2012 -0800

    i965: Double the push constant space multipliers on Broadwell too.
    
    Broadwell has 2Kb push constant size increments like Haswell GT3.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d48da0fcd2242affafa7e3e447d235c38a7e48fe
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Nov 1 16:29:33 2013 -0700

    i965: Update 3DSTATE_CLIP for Broadwell.
    
    Broadwell doesn't have GEN6_CLIP_Z_TEST, and doesn't make you specify
    the polygon winding information (it pulls that information from other
    packets).
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ff1e43f5f3ba1754cb1ee9198812eec0a52174d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Dec 3 18:28:29 2012 -0800

    i965: Rework vertex uploads for Broadwell.
    
    v2: Emit a dummy 3DSTATE_VF_SGVS packet when not needed.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7e2a58a37e80a224df066993e8e49f9b64221a4
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Dec 3 15:28:39 2012 -0800

    i965: Update invariant state for Broadwell.
    
    The only difference is that STATE_SIP takes a 48-bit address, so we need
    to output two zeroes.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=144c864515e2f9b61b611511822093ac269368e2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Dec 3 13:53:40 2012 -0800

    i965: Update STATE_BASE_ADDRESS for Broadwell.
    
    v2: Fix missing "change" bit on instruction state base address
        (caught by Haihao Xiang).
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=81a72c141fe227e6e252213692cdadb7c81d53d9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Nov 29 21:00:27 2012 -0800

    i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
    
    v2: Fix setting of GEN8_PSX_ATTRIBUTE_ENABLE after rebases.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=09fa6277fad75063bcec8efb777547b31179b09d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Nov 29 01:10:19 2012 -0800

    i965: Rework 3DSTATE_VS for Broadwell.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=99478c776743b049e6fccb8dcf1c43b579be8826
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Nov 29 18:43:59 2012 -0800

    i965: Add the new 3DSTATE_PS_BLEND state packet.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=41aa087d6069f544a627a2cb5dc3a73171ddc926
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Nov 29 17:52:31 2012 -0800

    i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6417177c6120f999f222984daa34855d197c7bab
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Nov 1 14:37:33 2013 -0700

    i965: Update SF, SBE, and RASTER state for Broadwell.
    
    The attribute override portion of 3DSTATE_SBE was split out into
    3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
    3DSTATE_RASTER.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=921805361d2c24e732ad93f05f7720fc92aa87cf
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Mon Nov 4 16:55:26 2013 -0800

    i965: Introduce an OUT_RELOC64 macro.
    
    Broadwell uses 48-bit addresses.  The first DWord is the low 32 bits,
    and the second DWord is the high 16 bits.
    
    Since individual buffers shouldn't be larger than 4GB in size, any
    offsets into those buffers (buffer->offset + delta) should fit in the
    low 32 bits.  So I believe we can simply emit 0 for the high 16-bits,
    and drm_intel_bo_emit_reloc() should patch it up.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=35b50092dfdabbab0edc34b6714da01341e24c09
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Nov 29 01:50:22 2012 -0800

    i965: Bump generation assertions on workaround flushes.
    
    These workaround flushes may not be necessary on Gen8.  Investigation is
    needed.  Tentatively, let's do them out of caution.
    
    v2: [chadv]
      - Comment that flush may not be needed.
      - Make assertion conditions symmetrical.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Chad Versace <chad.versace at linux.intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac1bf33ad5a00d63842ad377b79e467729efb8b5
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Nov 29 01:30:01 2012 -0800

    i965: Use the Sandybridge VUE format on Broadwell as well.
    
    It hasn't changed.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Chad Versace <chad.versace at linux.intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2c4641d7c8c3d10ce288104d5627c3acb163f57
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Nov 28 21:16:18 2012 -0800

    i965: Duplicate gen7_atoms to gen8_atoms.
    
    It's going to diverge significantly.  Starting out with a copy allows
    future patches to change atoms one by one.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f30f45134dfc693fba3f53052738a2c0a5ccfd8
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Nov 5 16:55:06 2013 -0800

    i965: Reserve space for "Vertex Count" in GS outputs.
    
    v2: Also increment ir->offset in the GS visitor, rather than at the
        final assembly generation stage (requested by Paul).
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf6f37e6e1d656ade9278025961166d9c2b6a81f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Dec 6 22:38:26 2012 -0800

    i965: Create a new fragment shader backend for Broadwell.
    
    This replaces the old fs_generator backend.
    
    v2: Port to the C-based representation of assembly instructions.
        Fix texturing after the texture-grf merge.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a96ff660d7afb0ca504a1adb111caee6d474d71e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Dec 6 22:37:34 2012 -0800

    i965: Create a new vec4 backend for Broadwell.
    
    This replaces the old vec4_generator backend.
    
    v2: Port to use the C-based instruction representation.  Also, remove
        Geometry Shader offset hacks - the visitor will handle those instead
        of this code.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e986a84e90bec2a75512da093e21b70e6adcc29
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Dec 6 22:36:50 2012 -0800

    i965: Add a new infrastructure for generating Broadwell shader assembly.
    
    This replaces the brw_eu_emit.c layer for Broadwell.  It will be
    used by both the vector and scalar shader backends.
    
    v2: Port to use the C-based instruction representation.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0de799fea533f84e9909c6e300a7fd63438f838
Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Dec 11 00:26:11 2012 -0800

    i965: Implement a disassembler for Broadwell's new instruction encoding
    
    Heavily based on Keith Packard's existing brw_disasm.c code.  I've tried
    to go through most of the pieces (like SFIDs) and update the lists to
    include features added in recent generations.
    
    v2: Port to use the C-based instruction emitters.  This allows us to use
        C99 array initializers, which tidies up some of the code.
    
    Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>