Mesa (broadwell): 157 new commits
Kenneth Graunke
kwg at kemper.freedesktop.org
Tue Dec 31 06:10:19 UTC 2013
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10b63e7ff8b84df200a1f0c89b6056c048637582
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 11:41:34 2013 -0700
i965: Add (disabled) Broadwell PCI IDs.
This puts the PCI IDs in place so it's easy to enable support. However,
it doesn't actually enable support since it's very preliminary still,
and a few crucial pieces (such as BLORP) are still missing.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=945df35e1f881fa1a7e42eb863688cc5cbaa226e
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 6 03:07:54 2013 -0800
i965: Disable 3DSTATE_WM_HZ_OP fields.
We'll need to do better than this when we implement multisampling, HiZ,
or fast clears...but for now, this will do.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0150129b4c1ad6b6efde55daa25c054661de42a0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 18 10:10:07 2013 -0800
i965: Fix MI_STORE_REGISTER_MEM for Broadwell.
It now takes a 48-bit address.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c9a0e8297508f3490b9bea8646932743dbb6cff
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 8 22:21:56 2013 -0800
i965: Fix up PIPE_CONTROL packets for Broadwell?
I believe these need to grow by 1 DWord for the AddressHigh bits.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e25475757148f6c0241716c8761ae858851baf99
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 8 22:21:29 2013 -0800
i965: Disable workaround flush for push constants on Broadwell.
If it wasn't necessary for Haswell, it's likely not to be necessary for
Broadwell either.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e897945cee76260bb13ac2b10484143624be7c1f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 11 18:30:32 2013 -0800
i965: Emit 3DSTATE_VF on Broadwell too.
It's not just for Haswell.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=69ec417564eacc085f7ceacf9fd980950fb1335d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 23:19:55 2013 -0800
i965: Update GS state for Broadwell.
This is quite similar to the Gen7 code. The main changes:
- 48-bit relocations
- Thread count is specified as U/2-1 instead of U-1.
- An extra DWord (DW9) with clip planes, URB entry output length/offsets
- We need to program the "Expected Vertex Count" (VerticesIn)
v2: Set the number of binding table entries so they can be prefetched
(requested by Eric Anholt).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=057d4b744e297e3b014a6f81b7345841ea7f7d24
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:20:37 2012 -0800
i965: Update multisampling state for Broadwell.
On previous platforms, 3DSTATE_MULTISAMPLE contained the number of
samples, pixel location, and the positions of each sample within a pixel
for each multisampling mode (4x and 8x). It was also a non-pipelined
command, presumably since changing the sample positions is fairly
drastic.
Broadwell improves upon this by splitting the sample positions out into
a separate non-pipelined state packet, 3DSTATE_SAMPLE_PATTERN. With
that removed, 3DSTATE_MULTISAMPLE becomes a pipelined state packet.
Broadwell also supports 2x and 16x multisampling, in addition to the 4x
and 8x supported by Gen7. This patch, however, does not implement 2x
and 16x.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b17ca96793e1566402963cbb4a3bc4bd924f949
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sat Jan 12 16:12:38 2013 -0800
i965: Update blitter code for 48-bit addresses.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e313ae621ba56746c4c5e1a169a35f6ec0db4a73
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 14 03:58:30 2012 -0800
i965: Update 3DSTATE_{DEPTH,STENCIL,...}_BUFFER and such for Broadwell.
XXX: Can probably just merge this in with the Gen7 code...
not really many changes. OUT_RELOC64 and a few extra DWords (Qpitch)
XXX: lots of these parameters are garbage...
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9adb9dd820d1ca1044feed7c5b8cc784b522b3f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 19:30:26 2012 -0800
i965: Update BLEND_STATE for Broadwell.
v2: Allow logic ops on all surface types. The UNORM restriction was
lifted with Haswell and I simply hadn't noticed. Also, add missing
BRW_NEW_STATE_BASE_ADDRESS dirty bit. Both caught by Eric Anholt.
v3: Fix swapped per-RT DWord pairs. Eliminates bizarre hacks.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76bd5d62b87d140f8acf2e18974ec6276b16037b
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 5 15:34:34 2012 -0800
i965: Update SF_CLIP_VIEWPORT for Broadwell.
It has more fields now. Not sure if this is correct for render_to_fbo.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ce739e0f6293ea1bdff0078d876cf89386204c7
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 16:39:03 2012 -0800
i965: Rework SURFACE_STATE entries for Broadwell.
v2: Add missing SCS setting in gen8_emit_buffer_surface_state (caught by
Eric Anholt).
v3: Use stored QPitch rather than recomputing it.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c78b097623a7031eccf9fee3c9112af46f56059
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 14:45:19 2012 -0800
i965: Update SOL state for Broadwell.
Unlike on Gen7, we can directly set the offset via the state packet.
We also -have- to: the kernel SOL reset code won't work anymore.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1cb89c33d85527f83c8194559c899677d7df3a0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:39:19 2012 -0800
i965: Update the code that disables unused shader stages for Broadwell.
v2: Also disable 3DSTATE_WM_CHROMAKEY for safety.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net> [v1]
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2c4ee270190b57fb7f5330b9719e0e719d69edd
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 4 11:39:14 2012 -0800
i965: Double the push constant space multipliers on Broadwell too.
Broadwell has 2Kb push constant size increments like Haswell GT3.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b90aa491fb7068a1570520b25758acafe99a6914
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 16:29:33 2013 -0700
i965: Update 3DSTATE_CLIP for Broadwell.
Broadwell doesn't have GEN6_CLIP_Z_TEST, and doesn't make you specify
the polygon winding information (it pulls that information from other
packets).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7c2012a46522b77b4c52d79b8ba139922a2b471
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 18:28:29 2012 -0800
i965: Rework vertex uploads for Broadwell.
v2: Emit a dummy 3DSTATE_VF_SGVS packet when not needed.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=172f5cd1287309a38320b1130413c28fc44f1f3c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 15:28:39 2012 -0800
i965: Update invariant state for Broadwell.
The only difference is that STATE_SIP takes a 48-bit address, so we need
to output two zeroes.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2635df84a1c9a96aafa7c0f9b8909ae8f56e7bb2
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 3 13:53:40 2012 -0800
i965: Update STATE_BASE_ADDRESS for Broadwell.
v2: Fix missing "change" bit on instruction state base address
(caught by Haihao Xiang).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=93bb895dbc2b04d8ca1d4b42de18e788d87989db
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 21:00:27 2012 -0800
i965: Update 3DSTATE_PS, 3DSTATE_WM, and add 3DSTATE_PS_EXTRA.
v2: Fix setting of GEN8_PSX_ATTRIBUTE_ENABLE after rebases.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d95e91fa393da5616b96b4eb4e5a7fac816a7df0
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:10:19 2012 -0800
i965: Rework 3DSTATE_VS for Broadwell.
v2: Remove incorrect MOCS shifts; rename urb_entry_write_offset to
urb_entry_output_offset to closer match the documentation.
v3: Only emit a non-zero constant buffer read length when active.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=400d5bc26463d4509f5f04445c2d2e0365440664
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 18:43:59 2012 -0800
i965: Add the new 3DSTATE_PS_BLEND state packet.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=969437ae5966b0414e5fcbacf8f6fdf8aa281c0d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 17:52:31 2012 -0800
i965: Replace DEPTH_STENCIL_STATE with Gen8's 3DSTATE_WM_DEPTH_STENCIL.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f214a1d1ac20dfa0d238991e8ec637ae134cdc55
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Nov 1 14:37:33 2013 -0700
i965: Update SF, SBE, and RASTER state for Broadwell.
The attribute override portion of 3DSTATE_SBE was split out into
3DSTATE_SBE_SWIZ; various bits of 3DSTATE_SF were split out into
3DSTATE_RASTER.
v2: Set Force URB Read Offset bit. Eventually the URB read offset
should be set in 3DSTATE_VS, but that will require some refactoring.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1681cb888db9a4dfebf42255300f49e2b74c548
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Nov 4 16:55:26 2013 -0800
i965: Introduce an OUT_RELOC64 macro.
Broadwell uses 48-bit addresses. The first DWord is the low 32 bits,
and the second DWord is the high 16 bits.
Since individual buffers shouldn't be larger than 4GB in size, any
offsets into those buffers (buffer->offset + delta) should fit in the
low 32 bits. So I believe we can simply emit 0 for the high 16-bits,
and drm_intel_bo_emit_reloc() should patch it up.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a09d762d306cd9d08b7b5a96c30521d7d9e6167
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:50:22 2012 -0800
i965: Bump generation assertions on workaround flushes.
These workaround flushes may not be necessary on Gen8. Investigation is
needed. Tentatively, let's do them out of caution.
v2: [chadv]
- Comment that flush may not be needed.
- Make assertion conditions symmetrical.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=65c322b8a5bdcdac9d66887e1fda24a671b3bdaa
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Nov 29 01:30:01 2012 -0800
i965: Use the Sandybridge VUE format on Broadwell as well.
It hasn't changed.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cb1237c796f662e0b4bbd9b80a057ba623a4338
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Nov 28 21:16:18 2012 -0800
i965: Duplicate gen7_atoms to gen8_atoms.
It's going to diverge significantly. Starting out with a copy allows
future patches to change atoms one by one.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b6f9fc898a66fbcb5d3155bf1f768e10bc4cf38
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 5 16:55:06 2013 -0800
i965: Reserve space for "Vertex Count" in GS outputs.
v2: Also increment ir->offset in the GS visitor, rather than at the
final assembly generation stage (requested by Paul).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cc56368d114ec92123df3975bd6b8f5322aec57
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:38:26 2012 -0800
i965: Create a new fragment shader backend for Broadwell.
This replaces the old fs_generator backend.
v2: Port to the C-based representation of assembly instructions.
Fix texturing after the texture-grf merge.
v3: Add high quality derivative support. Fix SET_SIMD4X2_OFFSET.
v4: Pass brw_context to gen8_instruction functions as required.
v5: Fixes for MRT, as well as zero render targets (alpha test only).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9c7d63a0042bf7cf40982ca1337d7174e8169eb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:37:34 2012 -0800
i965: Create a new vec4 backend for Broadwell.
This replaces the old vec4_generator backend.
v2: Port to use the C-based instruction representation. Also, remove
Geometry Shader offset hacks - the visitor will handle those instead
of this code.
v3: Texturing fixes (including adding textureGather support).
v4: Pass brw_context to gen8_instruction functions as required.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=332341fde4e8247b8d10e3101423abe01b04ea4d
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:50 2012 -0800
i965: Add a new infrastructure for generating Broadwell shader assembly.
This replaces the brw_eu_emit.c layer for Broadwell. It will be
used by both the vector and scalar shader backends.
v2: Port to use the C-based instruction representation.
v3: Fix destination register type for CMP.
v4: Pass brw to gen8_instruction functions (required by rebase).
v5: Remove bogus assertion on math instructions (caught by Piglit).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=06c88c0d9f10966e2489b8eb1643670ae4beff77
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 11 00:26:11 2012 -0800
i965: Implement a disassembler for Broadwell's new instruction encoding
Heavily based on Keith Packard's existing brw_disasm.c code. I've tried
to go through most of the pieces (like SFIDs) and update the lists to
include features added in recent generations.
v2: Port to use the C-based instruction emitters. This allows us to use
C99 array initializers, which tidies up some of the code.
v3: Improve decoding of render target write messages.
v4: Update for BRW_REGISTER_TYPE becoming an abstraction.
v5: Rebase on Chris Forbes' SFID message defines.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cdc3d2e45e38b54bdf6f2671ef24845e18153fc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Dec 6 22:36:26 2012 -0800
i965: Add a new representation for Broadwell shader instructions.
Broadwell significantly changes the EU instruction encoding. Many of
the fields got moved to different bit positions; some even got split
in two.
With so many changes, it was infeasible to continue using struct
brw_instruction. We needed a new representation.
This new approach is a bit different: rather than a struct, I created a
class that has four DWords, and helper functions that read/write various
bits. This has several advantages:
1. We can create several different names for the same bits. For
example, conditional modifiers, SFID for SEND instructions, and the
MATH instruction's function opcode are all stored in bits 27:24.
In each situation, we can use the appropriate setter function:
set_sfid(), set_math_function(), or set_cond_modifier(). This
is much easier to follow.
2. Since the fields are expressed using the original 128-bit numbers,
the code to create the getter/setter functions follows the table in
the documentation very closely.
To aid in debugging, I've enabled -fkeep-inline-functions when building
gen8_instruction.c. Otherwise, these functions cannot be called by
gdb, making it insanely difficult to print out anything.
Kenneth Graunke wrote most of this code. Damien Lespiau ported it to
C99. Xiang Haihao added media fields. Zhao Yakui added indirect
addressing support. Eric Anholt added an assertion to make sure that
values fit in the alloted number of bits.
v2: Update for brw_reg_type_to_hw_type(), which necessitates passing
brw_context pointers around everywhere.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
Signed-off-by: Xiang, Haihao <haihao.xiang at intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=57d9334811de5854479d92a0fb40219c31a25173
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 8 16:35:36 2013 -0800
i965: Add SFID #defines for media stuff.
While we probably won't ever use these, having them makes it easy to
share disassembler code between intel-gpu-tools and Mesa.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c13cfa8302084ae1b71506fbafe6da913a5807f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 8 16:33:19 2013 -0800
i965: Add #defines for new Broadwell math functions.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b6cc6fc573d337cd9c3ad00f53aa30dcfb98328
Author: Chris Forbes <chrisf at ijw.co.nz>
Date: Sun Nov 17 19:32:49 2013 +1300
i965: add struct and SFID for pixel interpolator messages
Signed-off-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f425d56ba41382be04366d011536ee78a03a2f33
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Sun Dec 29 23:19:36 2013 -0800
Revert "mesa: Remove GLXContextID typedef from glx.h."
This reverts commit 136a12ac98868d82c2ae9fcc80d11044a7ec56d1.
According to belak51 on IRC, this commit broke Allegro, which would no
longer compile. Applications apparently expect the GLXContextID typedef
to exist in glx.h; removing it breaks them. A bit of searching around
the internet revealed other complaints since upgrading to Mesa 10.
Cc: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da031f83f741b2d0182d3b05970093e9a73fbf58
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 26 22:22:13 2013 -0800
i965: Remove unused depth_mode parameter from translate_tex_format().
According to git blame, this hasn't been used in over two years:
commit d2235b0f4681f75d562131d655a6d7b7033d2d8b
Author: Eric Anholt <eric at anholt.net>
Date: Thu Nov 17 17:01:58 2011 -0800
i965: Always handle GL_DEPTH_TEXTURE_MODE through the shader.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=597a7ccc720037f302fdd047e5b17b61655bf6ca
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Dec 19 12:16:53 2013 +0200
i965/blorp: unit test compiling integer typed texture fetches
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c76b53482e7a2b0e056caed4653e10fc5f7afd9
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Dec 10 22:55:28 2013 +0200
i965/blorp: unit test compiling simple gen6 zero-src sampled
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=118c093d56384f7b36cd42c8f168f04a536640e7
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Dec 8 19:31:20 2013 +0200
i965/blorp: unit test compiling gen6 msaa-8 cms alpha blend
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b03319ddb1c48c5cd7b1002fa9eacc23df29851f
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Dec 8 19:26:47 2013 +0200
i965/blorp: unit test compiling bilinear filtered
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b928e345e483542c2d729dbc2c00fe08739e9fa2
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Dec 8 13:19:23 2013 +0200
i965/blorp: unit test compiling simple zero-src sampled
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=001b92c1121876ac73bc226e403af2f8952aca87
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Dec 8 13:06:35 2013 +0200
i965/blorp: unit test compiling unaligned msaa-8
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f89ebacbb1a3c55a70749c84f5f70bd033e4d11
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Dec 8 12:37:53 2013 +0200
i965/blorp: unit test compiling msaa-8 cms alpha blend
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=90dcf316313dfe0625c69867bcb036e7982b221d
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Dec 10 22:36:33 2013 +0200
i965/blorp: unit test compiling msaa-4 ums to cms
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11d2986a533f54d0ac379f234b360d9be8b07339
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Tue Dec 10 22:24:44 2013 +0200
i965/blorp: unit test compiling msaa-8 cms to cms
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=28d2c969e70f7ea26b876462893f59329fa2081d
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Sun Dec 8 11:25:55 2013 +0200
i965/blorp: unit test compiling msaa-8 ums to cms
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=812f1e94c0a4a9644b012851fb22a27efdbd26d0
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Dec 5 19:16:02 2013 +0200
i965/blorp: unit test compiling blend and scaled
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7757bf518d15f171d260784da9c655c4faef8e6
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Dec 5 17:59:29 2013 +0200
i965/blorp: allow unit tests to compile and dump assembly
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cb22f0da2e5f309a327e58f72dc25e5f864ff65
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Thu Dec 5 17:34:56 2013 +0200
i965: dump the disassembly to the given file
instead of ignoring the argument and always dumping to
standard output.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1958a9bbdf57dbcef0127012ea61c8492dfcb8b8
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Wed Nov 27 16:21:11 2013 +0200
i965/fs: allow fs-generator use without gl_fragment_program
Prepares the generator to accept hand-crafted blorp programs.
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca53704f4be2d1c8317512b96fbc9540d2856f98
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date: Wed Nov 27 14:32:41 2013 +0200
i965/fs: generate fs programs also without any 8-width instructions
Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ab47b435319c05521bdfced6da6ce72850a2dd7
Author: Rob Clark <robclark at freedesktop.org>
Date: Mon Dec 23 09:59:42 2013 -0500
freedreno/a3xx: fix blend state corruption issue
Using RMW on banked context registers is not safe. The value read
could be the wrong one. So if there has been a DRAW_IDX launched,
the RMW must be preceded by a WAIT_FOR_IDLE to ensure the read part
of RMW sees the correct value.
To avoid unnecessary WFI's, keep track if there is a need for WFI,
and only emit one if needed. Furthermore, keep track if we even
need to update the register in the first place.
And to cut down on the amount of RMW to avoid excessive WFI's, at the
tiling/GMEM level we can always overwrite RB_RENDER_CONTROL, as the
state at beginning of draw/clear cmds (which we IB to) is always
undefined. In the draw/clear commands, we always still use RMW (with
WFI if needed), but only if the register value actually changes. (At
points where the current value cannot be known, the saved value is
reset to ~0, which includes bits outside of RBRC_DRAW_STATE, so there
never is chance for confusion.)
Signed-off-by: Rob Clark <robclark at freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=be01d7a905d827c3c0c222cab2430c6d4575429a
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Dec 20 20:48:18 2013 -0500
freedreno: prepare for hw binning
Actually assign VSC_PIPE's properly, which will be needed for tiling.
And introduce fd_tile for per-tile state (including the assignment of
tile to VSC_PIPE). This gives us the proper pipe setup that we'll
need for hw binning pass, and also cleans things up a bit by not having
to pass so many parameters around. And will also make it easier to
introduce different tiling patterns (since we may no longer render
tiles in a simple left-to-right top-to-bottom pattern).
Signed-off-by: Rob Clark <robclark at freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64fe0670664bc6f2c75cc1630aa07cef1898b8b5
Author: Rob Clark <robclark at freedesktop.org>
Date: Fri Dec 20 18:08:54 2013 -0500
freedreno: resync generated headers
Signed-off-by: Rob Clark <robclark at freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2d53fac1c5b18f5c9e95d39d4e2be4703b0b363
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Tue Dec 24 15:22:31 2013 -0500
r600g: fix SUMO2 pci id
0x9649 is sumo2, not sumo.
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
CC: "9.2" "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=35a34143026785e015adb906756651807de89bde
Author: Vinson Lee <vlee at freedesktop.org>
Date: Thu Dec 19 15:55:28 2013 -0800
scons: Add system library linker flags on LLVM 3.5.
llvn-3.5svn r197664 split out the linker flags from ldflags to
system-libs.
Signed-off-by: Vinson Lee <vlee at freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ddabe0d523416693f28e293d8d3d918bdb612ca
Author: Aaron Watry <awatry at gmail.com>
Date: Fri Nov 15 16:09:41 2013 -0600
r600/pipe: Stop leaking context->start_compute_cs_cmd.buf on EG/CM
Found while tracking down memory leaks in VDPAU playback
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=20446d0e535c0735489c8944e8d767e0fc74fc6e
Author: Aaron Watry <awatry at gmail.com>
Date: Fri Nov 15 16:07:31 2013 -0600
st/vdpau: Destroy context when initialization fails
Prevents a potential memory leak found when tracking down something else.
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=767b0f82c37f0370c05335120e50f0a534549109
Author: Aaron Watry <awatry at gmail.com>
Date: Fri Nov 8 13:59:59 2013 -0600
radeon/llvm: Free target data at end of optimization
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0bd858d7ff4a16228164e3157aca846edeb6c228
Author: Aaron Watry <awatry at gmail.com>
Date: Fri Nov 8 13:53:10 2013 -0600
r600/compute: Use the correct FREE macro when deleting compute state
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e19717d075bd26c16e12564ed578ff519a5ce57a
Author: Aaron Watry <awatry at gmail.com>
Date: Thu Dec 12 16:35:54 2013 -0600
r600/compute: Free compiled kernels when deleting compute state
v2: Remove unnecessary null pointer check
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c9a9205d96b5ac0718218bfa952a5b4b6ad939c
Author: Aaron Watry <awatry at gmail.com>
Date: Thu Dec 12 16:34:09 2013 -0600
radeon/compute: Stop leaking LLVMContexts in radeon_llvm_parse_bitcode
Previously we were creating a new LLVMContext every time that we called
radeon_llvm_parse_bitcode, which caused us to leak the context every time
that we compiled a CL program.
Sadly, we can't dispose of the LLVMContext at the point that it was being
created because evergreen_launch_grid (and possibly the SI equivalent) was
assuming that the context used to compile the kernels was still available.
Now, we'll create a new LLVMContext when creating EG/SI compute state, store
it there, and pass it to all of the places that need it.
The LLVM Context gets destroyed when we delete the EG/SI compute state.
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7653c19a3b1adae162864587a7ab1c17ab256e6
Author: Aaron Watry <awatry at gmail.com>
Date: Fri Nov 8 13:45:05 2013 -0600
pipe_loader/sw: close dev->lib when initialization fails
Prevents a memory leak.
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=862f55c29c50798942e58ea75c5294921c0489f8
Author: Aaron Watry <awatry at gmail.com>
Date: Fri Nov 8 10:15:44 2013 -0600
clover: Remove unused variable
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
CC: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7990ab58fa01cbebcefd63dd25af5fd6fdddf019
Author: Jonathan Liu <net147 at gmail.com>
Date: Sun Dec 15 18:24:00 2013 -0700
llvmpipe: use pipe_sampler_view_release() to avoid segfault
This fixes another case of faulting when freeing a pipe_sampler_view
that belongs to a previously destroyed context.
Cc: "10.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jonathan Liu <net147 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=670be71bd801fea876f7512865ed5f54340da9be
Author: Jonathan Liu <net147 at gmail.com>
Date: Sat Dec 14 07:15:00 2013 -0700
st/mesa: use pipe_sampler_view_release()
This fixes a crash where old_view->context was already freed in the
pipe_sampler_view_reference function contained in
src/gallium/auxiliary/utils/u_inlines.h. As a result, the
sampler_view_destroy function pointer contained 0xfeeefeee indicating
freed heap memory.
Cc: "10.0" <mesa-stable at lists.freedesktop.org>
Signed-off-by: Jonathan Liu <net147 at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b094b3b9f4c7b40056c31e3480ab7dc530da56e7
Author: Henri Verbeet <hverbeet at gmail.com>
Date: Sun Dec 15 12:23:38 2013 +0100
i915: Add support for gl_FragData[0] reads.
Similar to 556a47a2621073185be83a0a721a8ba93392bedb, without this reading from
gl_FragData[0] would cause a software fallback.
Bugzilla: https://bugs.winehq.org/show_bug.cgi?id=33964
Signed-off-by: Henri Verbeet <hverbeet at gmail.com>
Cc: 10.0 9.2 9.1 <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2efe7927d38983029784825fc4897e9b77aa237e
Author: Andreas Hartmetz <ahartmetz at gmail.com>
Date: Sat Dec 21 21:11:37 2013 +0100
radeonsi: Use htile_buffer for depth only when there is no stencil.
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=900ac63ee88a16b7fb7f0ca2b03a40259b8ebd84
Author: Niels Ole Salscheider <niels_ole at salscheider-online.de>
Date: Wed Dec 18 19:11:44 2013 +0100
winsys/radeon: remove superfluous distinction of cases
Signed-off-by: Niels Ole Salscheider <niels_ole at salscheider-online.de>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=852db050b9ab0a2e525e7495ba6343051ad1bc1c
Author: Mark Mueller <markkmueller at gmail.com>
Date: Fri Dec 20 19:14:08 2013 -0800
mesa: inline r200 radeon texture format macros to facility search and replace
Signed-off-by: Mark Mueller <MarkKMueller at gmail.com>
Signed-off-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcefdc9a595c52ade2be15e0f3a2f301fee3599c
Author: Lauri Kasanen <cand at gmx.com>
Date: Thu Dec 19 21:43:25 2013 +0200
mesa: Fix build to properly check for supported compiler flags
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72708
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Signed-off-by: Lauri Kasanen <cand at gmx.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=79f268978d2341205f03738a2bc981838c09d920
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 13 14:27:11 2013 -0800
mesa: It is not possible to have GLSL < 1.20
This hasn't been possible for a long time.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=49493224623d4a559337a5079532015f7db58e4a
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 13 14:15:11 2013 -0800
mesa: Clean up bad code formatting left from previous commit
Also s/_EXT// on enums that are now part of core.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a92b9e60aba8cd1fc5d935abc9fd8f37cae89168
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 13 14:10:34 2013 -0800
mesa: GL_EXT_packed_depth_stencil is not optional
Every driver supports it. All current and future Gallium drivers always
support it, and all existing classic drivers support it.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b66edff4355e27d97de750feceb0c0dd34b7719b
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 13 13:24:14 2013 -0800
radeon: Sort list of enabled extensions
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bf436e014cb220f80c56683ee949ad93b2116a0
Author: Ian Romanick <ian.d.romanick at intel.com>
Date: Wed Nov 13 13:17:28 2013 -0800
r200: Sort list of enabled extensions
Note that ARB_occlusion_query was previously enabled twice.
Signed-off-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe2079c4c014934d1a5dbc87733742fea5a619da
Author: Lauri Kasanen <cand at gmx.com>
Date: Sun Dec 15 12:37:55 2013 +0200
glx: Simplify __glxGetMscRate, it only needs the screen, not a drawable
Useful in its own right, but also needed for adaptive vsync.
No regressions in the piglit glx-oml-sync-control-getmscrate test.
Signed-off-by: Lauri Kasanen <cand at gmx.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Tested-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b5111398110f9ae374723ad6225ada1a0e60fd2
Author: Keith Packard <keithp at keithp.com>
Date: Sat Nov 23 21:58:14 2013 -0800
dri3: Rename DRI3_MAX_BACK to DRI3_NUM_BACK
It is the maximum number of back buffers, but the name is confusing and is
easily read as the maximum back buffer index. Chage to DRI3_NUM_BACK to make
the intended usage a bit clearer.
Signed-off-by: Keith Packard <keithp at keithp.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=547bcc4b571e303c562d99dde74b915e56da54c0
Author: Keith Packard <keithp at keithp.com>
Date: Fri Nov 22 05:41:38 2013 -0800
i965: Set fast color clear mcs_state on newly allocated image miptrees
Just copying code from the dri2 path to set up the fast color clear state.
This also removes a couple of bogus intel_region_reference calls.
Signed-off-by: Keith Packard <keithp at keithp.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c426fb08cfd973b255d6e97d99350efc38b740ed
Author: Keith Packard <keithp at keithp.com>
Date: Fri Nov 22 05:39:15 2013 -0800
i965: Correct check for re-bound buffer in intel_update_image_buffer
The buffer-object is the persistent thing passed through the loader, so when
updating an image buffer, check to see if it is already bound to the provided
bo. The region, on the other hand, is allocated separately for the miptree,
and so will never be the same as that passed back from the loader.
Signed-off-by: Keith Packard <keithp at keithp.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca2012a912dcd3d671071ad7472c8a7c570745f2
Author: Keith Packard <keithp at keithp.com>
Date: Mon Nov 25 21:10:02 2013 -0800
dri3: Clean up struct dri3_drawable
Move the depth field up with width and height.
Remove unused previous_time and frames fields.
Signed-off-by: Keith Packard <keithp at keithp.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=95b04850d0c578392288939723d8d56e4b600c93
Author: Keith Packard <keithp at keithp.com>
Date: Thu Nov 21 21:30:07 2013 -0800
dri3: Free resources when drawable is destroyed.
Always nice to clean up after ourselves.
Signed-off-by: Keith Packard <keithp at keithp.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=568a27588d13146d0fd7cb4e775e1ac0187e5e29
Author: Keith Packard <keithp at keithp.com>
Date: Thu Nov 21 20:22:16 2013 -0800
dri3: Switch to libxshmfence version 1.1
libxshmfence v1.0 foolishly used 'int32_t *' for the fence type, which
works when the fence is a linux futex. However, version 1.1
changes the exported datatype to 'struct xshmfence *'
Require libxshmfence version 1.1 and switch the API around.
Signed-off-by: Keith Packard <keithp at keithp.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f330481c3979724300881891dfa17e99a5698ab
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Nov 26 23:15:39 2013 -0800
i965: Use RED for depth texture formats rather than INTENSITY.
While looking through the documentation, I found this in the Sandybridge
PRM (Volume 4, Part 1, Page 140):
"Use of sample_c with SURFTYPE_CUBE surfaces is undefined with the
following surface formats: I24X8_UNORM, L24X8_UNORM, A24X8_UNORM,
I32_FLOAT, L32_FLOAT, A32_FLOAT."
I haven't observed this to be true, but it suggests that we may want to
use other formats.
We already perform DEPTH_TEXTURE_MODE swizzling in the shaders, and
don't rely on the surface format to splat things appropriately. So
using RED should work just as well as INTENSITY.
A few notes about the formats:
- R24_UNORM_X8_TYPELESS has the exact same properties as I24X8_UNORM.
- R16_UNORM and R32_FLOAT are additionally supported as a render target,
while the old I16_UNORM/I32_FLOAT formats are not.
- R32_FLOAT_X8X24_TYPELESS is not supported as a render target, while
the old format (R32G32_FLOAT) was. However, it shares the same
properties as the formats we use for Z24, so it should suffice.
This makes translate_tex_format and brw_blorp_surface_info::set
a bit more similar.
No Piglit changes on Sandybridge or Ivybridge. No oglconform changes on
Sandybridge.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a928816a1b717201f3b3cc998a42731b280e6ba
Author: Chad Versace <chad.versace at linux.intel.com>
Date: Fri Dec 20 04:39:03 2013 -0800
i965/gen6: Fix HiZ hang in WebGL Google Maps
Emitting flushes before depth and hiz resolves at the top of blorp's
state emission fixes the hang. Marchesin and I found the fix
experimentally, as opposed to adhering to a documented hardware
workaround. A more minimal fix likely exists, but this gets the job
done.
Fixes HiZ hangs in the new WebGL Google maps on Sandybridge Chrome OS.
Tested by zooming in and out continuously for 2 hours.
This patch is based on
https://chromium.googlesource.com/chromiumos/overlays/chromiumos-overlay/+/8bc07bb70163c3706fb4ba5f980e57dc942f56dd
CC: mesa-stable at lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70740
Signed-off-by: Stéphane Marchesin <marcheu at chromium.org>
Signed-off-by: Chad Versace <chad.versace at linux.intel.com>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b97fa1e75b77a8f5e8b963ea792afeb02efe0419
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Fri Dec 13 16:10:02 2013 -0800
i965: Store QPitch in intel_mipmap_tree.
Broadwell allows us to specify an arbitrary value for QPitch, rather
than baking a specific formula into the hardware and requiring software
to lay things out to match. The only restriction is that the software
provided QPitch needs to be large enough so successive array slices do
not overlap.
In order to support this flexibility, software needs to specify QPitch
in a bunch of packets. Storing QPitch makes that easy, and allows us to
adjust it in a single place should we wish to change it in the future.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e8e17ccd7a64fdde9b78d239d8a3c256006c984
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 10 01:53:26 2013 -0800
i965: Add support for Broadwell's new register types.
Broadwell introduces support for Q, UQ, and HF types. It also extends
DF support to allow immediate values.
Irritatingly, although HF and DF both support immediates, they're
represented by a different value depending on the register file.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15b9aa22d7d40456d59a9686be302ef0078e083f
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 10 01:49:18 2013 -0800
i965: Add BRW_REGISTER_TYPE_DF.
Ivybridge, Baytrail, and Haswell support double float register types,
but do not support them as immediate values.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54e91e742010728cbf6c5b8c00b6ca5019a63eb9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 10 00:33:56 2013 -0800
i965: Abstract BRW_REGISTER_TYPE_* into an enum with unique values.
On released hardware, values 4-6 are overloaded. For normal registers,
they mean UB/B/DF. But for immediates, they mean UV/VF/V.
Previously, we just created #defines for each name, reusing the same
value. This meant we could directly splat the brw_reg::type field into
the assembly encoding, which was fairly nice, and worked well.
Unfortunately, Broadwell makes this infeasible: the HF and DF types are
represented as different numeric values depending on whether the
source register is an immediate or not.
To preserve sanity, I decided to simply convert BRW_REGISTER_TYPE_* to
an abstract enum that has a unique value for each register type, and
write translation functions. One nice benefit is that we can add
assertions about register files and generations.
I've chosen not to convert brw_reg::type to the enum, since converting
it caused a lot of trouble due to C++ enum rules (even though it's
defined in an extern "C" block...).
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13454fc3dea4cd4ed1676a1aaf91d49c9a811a7c
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 10 01:36:37 2013 -0800
i965: Decode three-source register types directly.
Three-source instructions use a different encoding for register types
(and have a much more limited set to choose from).
Previously, we translated those into BRW_REGISTER_TYPE_* values, then
reused the existing reg_encoding mapping.
Doing it directly is more straightforward and actually less code.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e95a099373c7e3f3f5f0f2854bc4eb582724a0a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 10 01:21:54 2013 -0800
i965: Disassemble UV types, not UB types.
UB types have never been supported as immediates. On Gen4-5, register
encoding 4 is "Reserved." On Gen6+, it means UV.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d10242c5f7dd5913edbd0a12bed44ecddf226ff9
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 10 01:18:34 2013 -0800
i965: Add missing BRW_REGISTER_TYPE_UV.
Sandybridge added support for packed unsigned vectors.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51c9cfc296318760aab421a79da727acd0e36311
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Wed Dec 18 12:30:06 2013 -0800
i965: Fix 3DSTATE_PUSH_CONSTANT_ALLOC_PS packet creation.
When adding geometry shader support, we accidentally reversed the size
and offset parameters.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
Cc: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d0edf8e4c3c6c102cf5689a36d58532a1863676
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 9 16:06:51 2013 -0800
i965: Use {point_sprite,flat}_enable variable names instead of dw*.
Calling the local variables flat_enable and point_sprite_enable is
clearer than dw16 and such. It also matches the names used in
calculate_attr_overrides, which computes them.
v2: Add /* dw16 */ and /* dw10 */ comments, requested by Jordan.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23fc845f81f55332aef509b5eb0610bb6a0df4bc
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon Dec 9 15:58:35 2013 -0800
i965: Zero out {point_sprite,flat}_enables in calculate_attr_overrides.
calculate_attr_overrides is responsible for computing the point sprite
and flat-shading enable bitfields. It does so by OR'ing in a bunch of
bits. However, it relied on the caller to set the initial value to
zero. This is pretty fragile - if the caller neglects to zero out those
variables, then the enable bitfields end up full of garbage, which shows
up as random things being flat-shaded.
This patch moves the zero-initialization into calculate_attr_overrides,
so that the computation is completely in one place.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da872ddcc610b50e30afe9cdd42f3ff5dc513e70
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Tue Dec 10 00:06:12 2013 -0800
i965: Delete bogus BRW_REGISTER_TYPE_HF define.
git blame ascribes this to the initial commit of the driver.
No released hardware has ever supported half float, according to the
documentation for SrcType in the ISA reference.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b1195f8a631d3425a418f846a6b9e0fa570c028
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Mon Dec 9 11:18:26 2013 +0200
Report that no function found if signature lookup is empty
If no function signature is found for a function name, report that the
function is not found instead of printing an empty list of candidates.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23d294bb60be41e3876179e7b763a275902d1efd
Author: Kevin Rogovin <kevin.rogovin at intel.com>
Date: Mon Dec 9 10:38:35 2013 +0200
Use line number information from entire function expression
This patch changes the error reporting behavior for incorrect function
invocation (triggered by match_function_by_name() unable to find a
matching function call) from using the line number information
associated to the function name term to using the line number
information of the entire function expression. Fixes bug #72264.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72264
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Cc: "10.0" <mesa-stable at lists.freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d58090500017dccec9e0991318881057455bc367
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Thu Dec 19 11:36:52 2013 +0900
radeonsi: Only scan pixel shaders for TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
It's not relevant for other shader types.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8252847b7b283ed7f7c514ce44246a2926a0add2
Author: Aaron Watry <awatry at gmail.com>
Date: Thu Dec 19 12:40:13 2013 -0600
r600g: Fix spelling error
Trivial change, testing commit access
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1413a09f346f7b0765b303f7770ec597c78bff2f
Author: Quanxian Wang <quanxian.wang at intel.com>
Date: Wed Dec 18 22:11:00 2013 -0700
egl: break instead of looping after driver is found
Stop searching for a driver after success.
Signed-off-by: Quanxian Wang <quanxian.wang at intel.com>
Reviewed-By: Gong, Zhigang <zhigang.gong at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=22bf0f3eb4668044042cdf326ccee29fa44f850a
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Thu Dec 19 05:27:00 2013 -0700
mesa: Assert variable coming from get_variable() in get_current_attrib
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7d8607d9ea4bfba31bd4eac00ab9a021db538e4
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Thu Dec 19 05:27:00 2013 -0700
mesa: Add asserts into emit_fog_instructions
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd6aaf2920ae69d743e5efe62bc26fa5ae678732
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Thu Dec 19 05:27:00 2013 -0700
glx: Fix two identical null check errors in driSet/GetInterval
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=149140e922a9fbf892c60a755788fb88d9757749
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Dec 18 18:00:33 2013 +1000
st_glsl_to_tgsi: add support for prim id fragment shader input
For GLSL 1.50 we can get frag shaders with primitive id as an
input, add support to the translator for this.
Reviewed-by: Brian Paul <brianp at vmware.com>
Signed-off-by: Dave Airlie <airlied at redhat.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=28b552bf6b7a0a79187db2887b25cbfa42cbf98b
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Wed Dec 18 06:58:00 2013 -0700
mesa: add asserts in load_texunit_bumpmap
In load_texunit_bumpmap tc_array is asserted so lets assert
rot_mat_0 and rot_mat_1 also which are coming from same path.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c02f6c26d32bc7ce6214bc9653b2c083fbed7dc7
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Wed Dec 18 06:58:00 2013 -0700
glx: add missing null check in dri2_bind_tex_image
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9bf5999d1a2b5ce59a5101582f838bbf147765d
Author: Brian Paul <brianp at vmware.com>
Date: Tue Dec 17 16:20:29 2013 -0700
mesa: minor simplification in _mesa_es3_error_check_format_and_type()
The type_valid local was set to true and never changed.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca3df5eeda1def6aa7e44fd136e2c17d3a061e87
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Mon Dec 16 07:04:00 2013 -0700
glx: Add missing null check in dri2CreateDrawable
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56c5ba8f92d372f6c36d1746e875bbba09b6b00f
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Mon Dec 16 07:04:00 2013 -0700
mesa: Verify memory allocations success in _mesa_PushAttrib
Check for malloc() returning null to fix Klocwork warnings.
Minor clean-ups by BrianP.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a83e4182c02f150ac278945f4519a615ec54f44
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Mon Dec 16 07:04:00 2013 -0700
mesa: Verify memory allocations success in _mesa_PushClientAttrib
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d08ac826c517f2a0a96c5e00d5c9bc4c223e6564
Author: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Date: Mon Dec 16 07:04:00 2013 -0700
mesa: Change save_attrib_data() to return boolean
Change save_attrib_data() to return true/false depending on success.
Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa4001b6075a5ca0c695f196e912f09ea12aed44
Author: Brian Paul <brianp at vmware.com>
Date: Mon Dec 16 09:41:09 2013 -0700
mesa: add API/extension checks for 3-component texture buffer formats
The GL_RGB32F, GL_RGB32UI and GL_RGB32I texture buffer formats are
only supposed to be allowed if the GL_ARB_texture_buffer_object_rgb32
extension is supported. Note that the texture buffer extensions
require a core profile. This patch adds those checks.
Fixes the soon-to-be-added
arb_clear_buffer_object-negative-bad-internalformat piglit test.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaaa9695b2c29bcebc670c8af74b54d70bc5cc7d
Author: Brian Paul <brianp at vmware.com>
Date: Mon Dec 16 09:40:03 2013 -0700
mesa: 78-column wrapping in extensions.c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bf3afdde900b66cdc5cc927f2efe3ee33c7be69
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: Cleanup mesa/main/bufferobj.h
Column wrapping and space between lines.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b0f5fc084c6994fb9e002e5fb9bf76f2d9f170a
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
Modify release notes to include ARB_clear_buffer_object extension
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78216fb48542ea82c19927bde83122ba6fd86e26
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
Add ARB_clear_buffer_object to list of supported extensions
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=787dadbeeaa26069799c7b0c8b17a4ce44f7e808
Author: Brian Paul <brianp at vmware.com>
Date: Mon Dec 16 09:06:17 2013 -0700
st/mesa: plug in default buffer object driver functions
In particular, this plugs in the new ClearBufferSubData() fallback
driver function.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f7bc0c75904a40da0973329badea8497e53a26a
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: Implement functions for clear_buffer_object extensions
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d94653052ab50af024ca9d37162084d454d9f80
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: Modify get_buffer() to allow for a variable error code
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84c4ea571d17a6798a0fae049a914b97165c56f7
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: Add bufferobj_range_mapped function
Add function to test if the buffer is already mapped and if so,
if the mapped range overlaps the given range.
Modify the _mesa_InvalidateBufferSubData function to use
the new function.
Enable buffer_object_subdata_range_good() to use bufferobj_range_mapped
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=72d872ad824110402a4455cb2b3aadb5c5160f89
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: get_texbuffer_format(): differentiate between core and compat context
alpha, lumincance and intensity formats are illegal in a core context.
Add a check to return MESA_FORMAT_NONE if one of those is requested within
a core context.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ec2d0a9a88214dd49ef6b864ec6e37f55c74535
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: Modify format validation to check for extension not context version
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5e6fe4d29fcada5f6f75eaff3160aa6ed4a46e3
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: Make validate_texbuffer_format function available externally
- change storage class from static to extern
- rename validate_texbuffer_format to _mesa_validate_texbuffer_format
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f7c3e541fa8c16435d78585e8c2ee449de5e61a
Author: Pi Tabred <servuswiegehtz at yahoo.de>
Date: Sat Dec 14 10:32:00 2013 -0700
mesa: Add infrastructure for GL_ARB_clear_buffer_object
- add xml file for extension
- add reference in gl_API.xml
- add pointer to device driver function table (dd.h)
- update dispatch_sanity.cpp
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56647c5d8f8e60269f0a3277e3caa7ee57d1fe6a
Author: Jan Vesely <jan.vesely at rutgers.edu>
Date: Sun Dec 15 17:28:16 2013 -0500
clover: Append buffers that use CL_MEM_USE_HOST_PTR.
Specs say it's legal for implementations to use internal copies, and
the write synchronization seems to work. Fixes clCreateBuffer
(together with previous patches) and buffer-flags piglits.
Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
Acked-by: Francisco Jerez <currojerez at riseup.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21f82188ce389a2543c894dd6d88fbebb25cc796
Author: Jan Vesely <jan.vesely at rutgers.edu>
Date: Tue Dec 17 11:19:09 2013 -0500
clover: Add parameter checks to clCreateBuffer.
v2: Use fewer if statements and functional tricks instead of single-use method,
suggested by Francisco Jerez.
Squash two small patches into one.
Signed-off-by: Jan Vesely <jan.vesely at rutgers.edu>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78fcc31d4a8179ca24a8008a1ad1ca6bdb668fdd
Author: Markus Trippelsdorf <markus at trippelsdorf.de>
Date: Fri Dec 13 10:59:42 2013 +0100
configure.ac: remove -fcolor-diagnostics from LLVM flags
When LLVM is build with Clang, "llvm-config --cxxflags" contains the
-fcolor-diagnostics flag. It is not recognized by gcc and the build
fails. Fix by removing the flag.
Signed-off-by: Markus Trippelsdorf <markus at trippelsdorf.de>
Signed-off-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=00cf048b12a82f1cde066c12bea63a9f20f5f216
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Tue Dec 17 05:44:38 2013 -0800
st/dri: Check for kernel support before enabling fd sharing v2
The dri2 state tracker is checking for driver support before enabling
dri2ImageExtension version 7. This commit adds a check that also the
kernel driver supports fd sharing through prime.
Note that this adds a libdrm dependency on dri2.c.
v2: Removed unnecessary clamping of bool expression
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Christopher James Halse Rogers <christopher.halse.rogers at canonical.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=37c24e6d867606e176a5164fc7ef1857862e76f8
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Dec 17 13:27:56 2013 +0100
radeonsi: set CB_DISABLE if the color mask is 0
Also needed for the DB in-place decompression according to hw docs.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3352ff97c29a4ff3de594504886765a603899739
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Dec 17 12:45:03 2013 +0100
radeonsi: add the htile buffer to the CS ioctl buffer list
This may fix the GPU crashes.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7963fde37b6646aef7868f9d552960e5967dd811
Author: Paul Berry <stereotype441 at gmail.com>
Date: Mon Dec 16 13:09:20 2013 -0800
glsl: Replace _mesa_glsl_parser_targets enum with gl_shader_type.
These enums were redundant.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=abab4385437bdcfbfff1cf772a5c418eb06ed822
Author: Paul Berry <stereotype441 at gmail.com>
Date: Mon Dec 16 13:05:09 2013 -0800
main: Move MESA_SHADER_TYPES outside of gl_shader_type enum.
This will avoid spurious compiler warnings in the patch that follows.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9b55244fd56b5971b40fdadb262a25840197096
Author: Paul Berry <stereotype441 at gmail.com>
Date: Mon Dec 16 12:58:55 2013 -0800
glsl: Don't return bad values from _mesa_shader_type_to_index.
This will avoid compiler warnings in the patch that follows. There
should be no user-visible effect because the change only affects the
behaviour when an invalid enum is passed to
_mesa_shader_type_to_index(), and that can only happen if there is a
bug elsewhere in Mesa.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=188630dc13b52ce9c64166da9a9df6a644b1599c
Author: Brian Paul <brianp at vmware.com>
Date: Fri Dec 13 15:55:28 2013 -0800
swrast: silence driContextSetFlags() parameter type warning
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d79058d1c6fb9fec71e866f29338b388291eb256
Author: Brian Paul <brianp at vmware.com>
Date: Fri Dec 13 15:54:45 2013 -0800
st/dri: fix compiler warning for driCopySubBufferExtension
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b404a650493514896b345e70713c1c3bbe58a26
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Dec 17 03:11:30 2013 +0100
radeonsi: improve HiZ precision for less and lequal depth functions
r600g needs this too.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a63f278f2d312937a6d429c2b39db5307fb46ab
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Dec 17 03:06:44 2013 +0100
radeonsi: make DB_RENDER_OVERRIDE an invariant register
All this cruft was ported from r600g and isn't needed on SI and later
according to hw docs. If we implemented HiS, we would set it to 0.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=249cb511c54d40a762c862a7e378a362db4a1ca0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Dec 17 00:46:45 2013 +0100
radeonsi: flush HTILE when appropriate
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e2b0f801d7c8d80f6c0d9da3813d7ed8b84e3dd
Author: Thomas Hellstrom <thellstrom at vmware.com>
Date: Thu Sep 20 11:41:23 2012 +0200
st/xa: Add new map flags
Replicate some of the gallium pipe transfer functionality.
Also bump minor to signal availability of this feature.
Signed-off-by: Thomas Hellstrom <thellstrom at vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=56d920a5c1b64868e77a97604c01d3a63916a6ca
Author: Alexander von Gluck IV <kallisti5 at unixzen.com>
Date: Sat Dec 14 11:46:05 2013 -0600
Haiku: Add in public GL kit headers
* These make up the base of what C++ GL Haiku applications
use for 3D rendering.
* Not placed in includes/GL to prevent Haiku headers from
getting installed on non-Haiku systems.
Acked-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9cfe5ce82cf49fec5603db42324df40372ee671
Author: Rob Clark <robclark at freedesktop.org>
Date: Sat Dec 14 12:13:28 2013 -0500
freedreno: dummy-draw workaround for a320
Fixes gpu lockups in supertuxkart.
Signed-off-by: Rob Clark <robclark at freedesktop.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b56c7f4df118a4a178988cb6c07154b56e6788db
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Dec 12 17:22:52 2013 +0100
r600g: expose 32-bit integer vertex formats
This advertises GL_ARB_texture_buffer_object_rgb32.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eb321b992183bfa7a84209ff059f1e2b902247e
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Dec 5 19:39:36 2013 +0100
radeonsi: move invariant regs to si_init_config
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=696229523d919de15ebc25d0f475bf56d7dad4a9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Dec 12 18:09:08 2013 +0100
r600g: use shader-based MSAA resolving when hw-based one cannot be used
This fixes some MSAA integer tests.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ebb9a3c8e0d93bae2408daae3cb8b1045e0a473
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Dec 7 17:57:10 2013 +0100
radeonsi: use shader-based MSAA resolving when hw-based one cannot be used
This fixes MSAA resolving for 32-bit integer colorbuffers, which isn't
implemented by the hardware.
It also fixes VM protection faults when resolving MSAA 2D array textures.
This may be a CB bug, because shader-based resolving works fine.
It may also be faster for upside-down and scaled blits.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a609fbcb5459fc5cac2e0361a405ea4b884325f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Dec 7 17:32:22 2013 +0100
gallium/u_blitter: implement shader-based MSAA resolve with bilinear filtering
For scaled resolve. The filter is only good for magnification.
If somebody has an idea how to implement a good filter for minification,
I'm all ears. I'd have to use derivatives probably.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc21098a95c8f7d0aadbfcc90cb2e9e78d1e2ef3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Dec 6 23:55:05 2013 +0100
gallium/u_blitter: implement shader-based MSAA resolve
We need this for integer formats and upside-down blits, which Radeons don't
support for MSAA resolving.
It can be used by calling util_blitter_blit.
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0ed082babe29eee502ec81302dae5fc15347e3f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Fri Dec 6 22:39:48 2013 +0100
gallium/u_blitter: remove useless parameters from some functions
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=072c5d0573dff817dbd7eb0f2f458167ec46bebb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Dec 10 17:46:41 2013 +0100
st/dri: resolve sRGB buffers in linear colorspace
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=27d47bd42f417db96842c9453092acf68944a4c8
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Dec 13 21:20:05 2013 +0100
gallivm: fix pointer type for stmxcsr/ldmxcsr
The argument is a i8 pointer not a i32 pointer (even though the value actually
stored/loaded IS i32). Older llvm versions didn't care but 3.2 and newer do
leading to crashes.
Reviewed-by: Zack Rusin <zackr at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c027666da1cd3691983bbc238847a2af57f336e
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Dec 13 18:31:07 2013 +0100
llvmpipe: get rid of barycentric calculation of a0
Didn't really work as well as hoped (in particular it was not generally
more accurate), will solve this differently.
Reviewed-by: Jose Fonseca <jfonseca at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfcf1ba1c4879102eb05460528b02a23d81eac99
Author: Roland Scheidegger <sroland at vmware.com>
Date: Fri Dec 13 01:09:35 2013 +0100
llvmpipe: (trivial) get rid of triangle subdivision code
This code was always problematic, and with 64bit rasterization we no longer
need it at all.
Reviewed-by: Zack Rusin <zackr at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
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