Mesa (master): i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.

[Paul Berry]

Module: Mesa
Branch: master
Commit: 460b7bc7a103d7a7518b4187f0c1dfc452f75137
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=460b7bc7a103d7a7518b4187f0c1dfc452f75137

Author: Paul Berry <stereotype441 at gmail.com>
Date:   Wed May  1 07:16:52 2013 -0700

i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.

On Gen7+, MCS buffers are used both for compressed multisampled color
buffers and for "fast clear" of single-sampled color buffers.

Previous to this patch series, we didn't support fast clear, so we
only used MCS with multisampled bolor buffers.

As a first step to implementing fast clears, this patch modifies the
code that sets up SURFACE_STATE so that it configures the MCS buffer
whenever it is present, regardless of whether we are multisampling or
not.

Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/gen7_blorp.cpp          |    2 +-
 src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |    2 +-
 src/mesa/drivers/dri/intel/intel_mipmap_tree.h    |    8 +++++---
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 68c7ca1..208c66a 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -194,7 +194,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
    surf[3] = pitch_bytes - 1;
 
    surf[4] = gen7_surface_msaa_bits(surface->num_samples, surface->msaa_layout);
-   if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+   if (surface->mt->mcs_mt) {
       gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
                                 is_render_target);
    }
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 6a7c8de..3164f99 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -609,7 +609,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
              min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
              (depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
 
-   if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+   if (irb->mt->mcs_mt) {
       gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
                                 irb->mt->mcs_mt, true /* is RT */);
    }
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index d66d0b5..e2a7fe8 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -443,11 +443,13 @@ struct intel_mipmap_tree
 
 #ifndef I915
    /**
-    * \brief MCS miptree for multisampled textures.
+    * \brief MCS miptree.
     *
     * This miptree contains the "multisample control surface", which stores
-    * the necessary information to implement compressed MSAA on Gen7+
-    * (INTEL_MSAA_FORMAT_CMS).
+    * the necessary information to implement compressed MSAA
+    * (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
+    *
+    * NULL if no MCS miptree is in use for this surface.
     */
    struct intel_mipmap_tree *mcs_mt;