Mesa (9.1): r600g: Use blitter rather than DMA for 128bpp on cayman (v3)

[Alex Deucher]

Module: Mesa
Branch: 9.1
Commit: d0ccb5b91191251c2a76ef43819c0a7704cecaba
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0ccb5b91191251c2a76ef43819c0a7704cecaba

Author: Alex Deucher <alexander.deucher at amd.com>
Date:   Fri Mar 15 14:29:24 2013 -0400

r600g: Use blitter rather than DMA for 128bpp on cayman (v3)

On cayman, 128bpp surfaces require non_disp ordering for hw
access to both linear and tiled surfaces.  When we use the 3D
engine we can set the non_disp ordering on both the tiled and
linear sides (via CB or texture), but when we use the DMA
engine, we can only set the non_disp ordering on the tiled
side, so after a L2T operation with the DMA engine, the data
ends up in the wrong order on the tiled side.

v2: cayman/TN only

v3: fix comments

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60802

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
(cherry picked from commit 4409758a046a47b09cdd339f97afd22107c68f0c)

---

 src/gallium/drivers/r600/evergreen_state.c |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 33f306c..804c037 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3676,6 +3676,17 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
 		return FALSE;
 	}
 
+	/* 128 bpp surfaces require non_disp_tiling for both
+	 * tiled and linear buffers on cayman.  However, async
+	 * DMA only supports it on the tiled side.  As such
+	 * the tile order is backwards after a L2T/T2L packet.
+	 */
+	if ((rctx->chip_class == CAYMAN) &&
+	    (src_mode != dst_mode) &&
+	    (util_format_get_blocksize(src->format) >= 16)) {
+		return FALSE;
+	}
+
 	if (src_mode == dst_mode) {
 		uint64_t dst_offset, src_offset;
 		/* simple dma blit would do NOTE code here assume :