Mesa (9.1): radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE
Michel Dänzer
daenzer at kemper.freedesktop.org
Thu May 23 08:53:49 UTC 2013
Module: Mesa
Branch: 9.1
Commit: 3db274fbd150aedfadb0a1b4e6cec63929c56a1b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3db274fbd150aedfadb0a1b4e6cec63929c56a1b
Author: Michel Dänzer <michel.daenzer at amd.com>
Date: Fri May 3 17:59:34 2013 +0200
radeonsi: Fix handling of TGSI_SEMANTIC_PSIZE
Two more little piglits.
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit 4730dea5f5ddd5f94091aeb423c0e0cce4e64fdb)
---
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 1 -
src/gallium/drivers/radeonsi/radeonsi_shader.c | 4 +++-
src/gallium/drivers/radeonsi/radeonsi_shader.h | 2 ++
src/gallium/drivers/radeonsi/si_state.c | 4 ----
src/gallium/drivers/radeonsi/si_state_draw.c | 15 ++++++++++++---
5 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
index 8c6d908..0fe5cfb 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -126,7 +126,6 @@ struct r600_context {
unsigned pa_sc_line_stipple;
unsigned pa_su_sc_mode_cntl;
unsigned pa_cl_clip_cntl;
- unsigned pa_cl_vs_out_cntl;
/* for saving when using blitter */
struct pipe_stencil_ref stencil_ref;
struct si_pipe_shader_selector *ps_shader;
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index ac654e6..c6d86ec 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -650,7 +650,9 @@ static void si_llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
/* Select the correct target */
switch(d->Semantic.Name) {
case TGSI_SEMANTIC_PSIZE:
- target = V_008DFC_SQ_EXP_POS;
+ shader->vs_out_misc_write = 1;
+ shader->vs_out_point_size = 1;
+ target = V_008DFC_SQ_EXP_POS + 1;
break;
case TGSI_SEMANTIC_POSITION:
if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.h b/src/gallium/drivers/radeonsi/radeonsi_shader.h
index 7960fc9..37e1f55 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.h
@@ -74,6 +74,8 @@ struct si_shader {
unsigned ninterp;
bool uses_kill;
bool fs_write_all;
+ bool vs_out_misc_write;
+ bool vs_out_point_size;
unsigned nr_cbufs;
};
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 79fed67..7085fb4 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -411,9 +411,6 @@ static void *si_create_rs_state(struct pipe_context *ctx,
S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
- rs->pa_cl_vs_out_cntl =
- S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
- S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
@@ -484,7 +481,6 @@ static void si_bind_rs_state(struct pipe_context *ctx, void *state)
rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
- rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
si_pm4_bind_state(rctx, rasterizer, rs);
si_update_fb_rs_state(rctx);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index 93766a3..ed5d6e0 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -55,8 +55,13 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
* takes care of adding a dummy export.
*/
for (nparams = 0, i = 0 ; i < shader->shader.noutput; i++) {
- if (shader->shader.output[i].name != TGSI_SEMANTIC_POSITION)
+ switch (shader->shader.output[i].name) {
+ case TGSI_SEMANTIC_POSITION:
+ case TGSI_SEMANTIC_PSIZE:
+ break;
+ default:
nparams++;
+ }
}
if (nparams < 1)
nparams = 1;
@@ -66,7 +71,9 @@ static void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *s
si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
- S_02870C_POS1_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
+ S_02870C_POS1_EXPORT_FORMAT(shader->shader.vs_out_misc_write ?
+ V_02870C_SPI_SHADER_4COMP :
+ V_02870C_SPI_SHADER_NONE) |
S_02870C_POS2_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE) |
S_02870C_POS3_EXPORT_FORMAT(V_02870C_SPI_SHADER_NONE));
@@ -258,6 +265,7 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
const struct pipe_draw_info *info)
{
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_shader *vs = &rctx->vs_shader->current->shader;
unsigned prim = si_conv_pipe_prim(info->mode);
unsigned ls_mask = 0;
@@ -296,7 +304,8 @@ static bool si_update_draw_info_state(struct r600_context *rctx,
si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL, rctx->pa_su_sc_mode_cntl);
}
si_pm4_set_reg(pm4, R_02881C_PA_CL_VS_OUT_CNTL,
- prim == PIPE_PRIM_POINTS ? rctx->pa_cl_vs_out_cntl : 0
+ S_02881C_USE_VTX_POINT_SIZE(vs->vs_out_point_size) |
+ S_02881C_VS_OUT_MISC_VEC_ENA(vs->vs_out_misc_write)
/*| (rctx->rasterizer->clip_plane_enable &
rctx->vs_shader->shader.clip_dist_write)*/);
si_pm4_set_reg(pm4, R_028810_PA_CL_CLIP_CNTL, rctx->pa_cl_clip_cntl
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