Mesa (master): i965/fs: Fix message setup for SIMD8 spills.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: 7c90947a0ba7f61b58a6fd5b94a08587e68d978e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c90947a0ba7f61b58a6fd5b94a08587e68d978e

Author: Eric Anholt <eric at anholt.net>
Date:   Mon Nov  4 22:56:33 2013 -0800

i965/fs: Fix message setup for SIMD8 spills.

In the SIMD16 spilling changes, I replaced a "1" in the spill path with
"mlen", but obviously it wasn't mlen before because spills have the g0
header along with the payload. The interface I was trying to use was
asking for how many physical regs we're writing, so we're looking for "1"
or "2".

I'm guessing this actually passed piglit because the high 8 bits of the
execution mask in SIMD8 mode are all 0s.

Cc: "10.0" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Paul Berry <stereotype441 at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 6678553..cc58ff2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -757,7 +757,7 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
 	   retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD),
 	   retype(src, BRW_REGISTER_TYPE_UD));
    brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf),
-                                 inst->mlen, inst->offset);
+                                 dispatch_width / 8, inst->offset);
 }
 
 void