Mesa (9.2): i965: Move post-sync non-zero flush for 3DSTATE_MULTISAMPLE.
Carl Worth
cworth at kemper.freedesktop.org
Wed Nov 13 01:01:17 UTC 2013
Module: Mesa
Branch: 9.2
Commit: 95a708abe6a814918552a104bd162a16fc2e104a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=95a708abe6a814918552a104bd162a16fc2e104a
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Thu Oct 24 00:38:27 2013 -0700
i965: Move post-sync non-zero flush for 3DSTATE_MULTISAMPLE.
For some reason, we put the flush in the caller, rather than just before
emitting the packet. This is more than a cosmetic problem: BLORP calls
gen6_emit_3dstate_multisample() directly, and so it missed the flush.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Xinkai Chen <yeled.nova at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Cc: "9.2" <mesa-stable at lists.freedesktop.org>
(cherry picked from commit 65b1f642ac2dff58498622bf6e0b7be8d9d3e20d)
---
src/mesa/drivers/dri/i965/gen6_multisample_state.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index 268dc79..a76ab1e 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -128,6 +128,9 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
break;
}
+ /* 3DSTATE_MULTISAMPLE is nonpipelined. */
+ intel_emit_post_sync_nonzero_flush(brw);
+
int len = brw->gen >= 7 ? 4 : 3;
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
@@ -183,9 +186,6 @@ static void upload_multisample_state(struct brw_context *brw)
}
}
- /* 3DSTATE_MULTISAMPLE is nonpipelined. */
- intel_emit_post_sync_nonzero_flush(brw);
-
gen6_emit_3dstate_multisample(brw, num_samples);
gen6_emit_3dstate_sample_mask(brw, num_samples, coverage,
coverage_invert, sample_mask);
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