Mesa (master): i965: Add Gen assertion checks for newer instructions.

[Matt Turner]

Module: Mesa
Branch: master
Commit: 69909c866b6595f80d206c8e2484b1dc6668e7be
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=69909c866b6595f80d206c8e2484b1dc6668e7be

Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu Sep 19 22:55:24 2013 -0700

i965: Add Gen assertion checks for newer instructions.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   |   11 +++++++++++
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |   11 +++++++++++
 2 files changed, 22 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 8fe4203..a35c172 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1244,6 +1244,7 @@ fs_generator::generate_code(exec_list *instructions)
 	 break;
 
       case BRW_OPCODE_MAD:
+         assert(brw->gen >= 6);
 	 brw_set_access_mode(p, BRW_ALIGN_16);
 	 if (dispatch_width == 16) {
 	    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
@@ -1258,6 +1259,7 @@ fs_generator::generate_code(exec_list *instructions)
 	 break;
 
       case BRW_OPCODE_LRP:
+         assert(brw->gen >= 6);
 	 brw_set_access_mode(p, BRW_ALIGN_16);
 	 if (dispatch_width == 16) {
 	    brw_set_compression_control(p, BRW_COMPRESSION_NONE);
@@ -1306,9 +1308,11 @@ fs_generator::generate_code(exec_list *instructions)
 	 brw_SHL(p, dst, src[0], src[1]);
 	 break;
       case BRW_OPCODE_F32TO16:
+         assert(brw->gen >= 7);
          brw_F32TO16(p, dst, src[0]);
          break;
       case BRW_OPCODE_F16TO32:
+         assert(brw->gen >= 7);
          brw_F16TO32(p, dst, src[0]);
          break;
       case BRW_OPCODE_CMP:
@@ -1318,19 +1322,23 @@ fs_generator::generate_code(exec_list *instructions)
 	 brw_SEL(p, dst, src[0], src[1]);
 	 break;
       case BRW_OPCODE_BFREV:
+         assert(brw->gen >= 7);
          /* BFREV only supports UD type for src and dst. */
          brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
                       retype(src[0], BRW_REGISTER_TYPE_UD));
          break;
       case BRW_OPCODE_FBH:
+         assert(brw->gen >= 7);
          /* FBH only supports UD type for dst. */
          brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
          break;
       case BRW_OPCODE_FBL:
+         assert(brw->gen >= 7);
          /* FBL only supports UD type for dst. */
          brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
          break;
       case BRW_OPCODE_CBIT:
+         assert(brw->gen >= 7);
          /* CBIT only supports UD type for dst. */
          brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
          break;
@@ -1348,6 +1356,7 @@ fs_generator::generate_code(exec_list *instructions)
          break;
 
       case BRW_OPCODE_BFE:
+         assert(brw->gen >= 7);
          brw_set_access_mode(p, BRW_ALIGN_16);
          if (dispatch_width == 16) {
             brw_set_compression_control(p, BRW_COMPRESSION_NONE);
@@ -1362,9 +1371,11 @@ fs_generator::generate_code(exec_list *instructions)
          break;
 
       case BRW_OPCODE_BFI1:
+         assert(brw->gen >= 7);
          brw_BFI1(p, dst, src[0], src[1]);
          break;
       case BRW_OPCODE_BFI2:
+         assert(brw->gen >= 7);
          brw_set_access_mode(p, BRW_ALIGN_16);
          if (dispatch_width == 16) {
             brw_set_compression_control(p, BRW_COMPRESSION_NONE);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index ae6e43c..67af0dd 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -873,6 +873,7 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       break;
 
    case BRW_OPCODE_MAD:
+      assert(brw->gen >= 6);
       brw_MAD(p, dst, src[0], src[1], src[2]);
       break;
 
@@ -935,31 +936,38 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       break;
 
    case BRW_OPCODE_F32TO16:
+      assert(brw->gen >= 7);
       brw_F32TO16(p, dst, src[0]);
       break;
 
    case BRW_OPCODE_F16TO32:
+      assert(brw->gen >= 7);
       brw_F16TO32(p, dst, src[0]);
       break;
 
    case BRW_OPCODE_LRP:
+      assert(brw->gen >= 6);
       brw_LRP(p, dst, src[0], src[1], src[2]);
       break;
 
    case BRW_OPCODE_BFREV:
+      assert(brw->gen >= 7);
       /* BFREV only supports UD type for src and dst. */
       brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
                    retype(src[0], BRW_REGISTER_TYPE_UD));
       break;
    case BRW_OPCODE_FBH:
+      assert(brw->gen >= 7);
       /* FBH only supports UD type for dst. */
       brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
       break;
    case BRW_OPCODE_FBL:
+      assert(brw->gen >= 7);
       /* FBL only supports UD type for dst. */
       brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
       break;
    case BRW_OPCODE_CBIT:
+      assert(brw->gen >= 7);
       /* CBIT only supports UD type for dst. */
       brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
       break;
@@ -977,13 +985,16 @@ vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
       break;
 
    case BRW_OPCODE_BFE:
+      assert(brw->gen >= 7);
       brw_BFE(p, dst, src[0], src[1], src[2]);
       break;
 
    case BRW_OPCODE_BFI1:
+      assert(brw->gen >= 7);
       brw_BFI1(p, dst, src[0], src[1]);
       break;
    case BRW_OPCODE_BFI2:
+      assert(brw->gen >= 7);
       brw_BFI2(p, dst, src[0], src[1], src[2]);
       break;