Mesa (9.2): i965: Don't forget the cube map padding on gen5+.
Carl Worth
cworth at kemper.freedesktop.org
Wed Oct 16 22:10:51 UTC 2013
Module: Mesa
Branch: 9.2
Commit: eb69e251a8e6554555b921613eac222cae54ae4a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb69e251a8e6554555b921613eac222cae54ae4a
Author: Eric Anholt <eric at anholt.net>
Date: Tue Oct 8 00:20:04 2013 -0700
i965: Don't forget the cube map padding on gen5+.
We had a fixup for gen4's 3d-layout cubemaps (which, iirc, we'd
experimentally found to be necessary!), but while the spec still requires
it on gen5, we'd been missing it in the array-layout cubemaps.
Cc: "9.1 9.2" <mesa-stable at lists.freedesktop.org>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Chad Versace <chad.versace at linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
(cherry picked from commit 791550aa8e70dd5e0bdd5a996ef66b5964cf9095)
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 22 +++++++++++++++-------
1 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index ebc67b1..f695b15 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -205,6 +205,18 @@ brw_miptree_layout_2d(struct intel_mipmap_tree *mt)
}
static void
+align_cube(struct intel_mipmap_tree *mt)
+{
+ /* The 965's sampler lays cachelines out according to how accesses
+ * in the texture surfaces run, so they may be "vertical" through
+ * memory. As a result, the docs say in Surface Padding Requirements:
+ * Sampling Engine Surfaces that two extra rows of padding are required.
+ */
+ if (mt->target == GL_TEXTURE_CUBE_MAP)
+ mt->total_height += 2;
+}
+
+static void
brw_miptree_layout_texture_array(struct brw_context *brw,
struct intel_mipmap_tree *mt)
{
@@ -228,6 +240,8 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
}
}
mt->total_height = qpitch * mt->physical_depth0;
+
+ align_cube(mt);
}
static void
@@ -299,13 +313,7 @@ brw_miptree_layout_texture_3d(struct brw_context *brw,
}
}
- /* The 965's sampler lays cachelines out according to how accesses
- * in the texture surfaces run, so they may be "vertical" through
- * memory. As a result, the docs say in Surface Padding Requirements:
- * Sampling Engine Surfaces that two extra rows of padding are required.
- */
- if (mt->target == GL_TEXTURE_CUBE_MAP)
- mt->total_height += 2;
+ align_cube(mt);
}
void
More information about the mesa-commit
mailing list