Mesa (master): i965: Move flushing out of write_reg and into the callers.
Kenneth Graunke
kwg at kemper.freedesktop.org
Wed Oct 23 08:09:05 UTC 2013
Module: Mesa
Branch: master
Commit: d5db3ece0a5d1a543b55cce38e39543deadc82eb
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5db3ece0a5d1a543b55cce38e39543deadc82eb
Author: Kenneth Graunke <kenneth at whitecape.org>
Date: Mon May 27 19:44:44 2013 -0700
i965: Move flushing out of write_reg and into the callers.
The current callers just want to write a single register, so combining
the register read with a pipeline flush made sense. However, in the
future we'll want to do multiple register reads back to back, and we'll
only want to flush once.
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Eric Anholt <eric at anholt.net>
---
src/mesa/drivers/dri/i965/gen6_queryobj.c | 12 ++++++++----
1 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_queryobj.c b/src/mesa/drivers/dri/i965/gen6_queryobj.c
index 498b187..dd5cfc2 100644
--- a/src/mesa/drivers/dri/i965/gen6_queryobj.c
+++ b/src/mesa/drivers/dri/i965/gen6_queryobj.c
@@ -98,8 +98,10 @@ write_depth_count(struct brw_context *brw, drm_intel_bo *query_bo, int idx)
* Write an arbitrary 64-bit register to a buffer via MI_STORE_REGISTER_MEM.
*
* Only TIMESTAMP and PS_DEPTH_COUNT have special PIPE_CONTROL support; other
- * counters have to be read via the generic MI_STORE_REGISTER_MEM. This
- * function also performs a pipeline flush for proper synchronization.
+ * counters have to be read via the generic MI_STORE_REGISTER_MEM.
+ *
+ * Callers must explicitly flush the pipeline to ensure the desired value is
+ * available.
*/
static void
write_reg(struct brw_context *brw,
@@ -107,8 +109,6 @@ write_reg(struct brw_context *brw,
{
assert(brw->gen >= 6);
- intel_batchbuffer_emit_mi_flush(brw);
-
/* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
* read a full 64-bit register, we need to do two of them.
*/
@@ -131,6 +131,8 @@ static void
write_primitives_generated(struct brw_context *brw,
drm_intel_bo *query_bo, int idx)
{
+ intel_batchbuffer_emit_mi_flush(brw);
+
write_reg(brw, query_bo, CL_INVOCATION_COUNT, idx);
}
@@ -138,6 +140,8 @@ static void
write_xfb_primitives_written(struct brw_context *brw,
drm_intel_bo *query_bo, int idx)
{
+ intel_batchbuffer_emit_mi_flush(brw);
+
if (brw->gen >= 7) {
write_reg(brw, query_bo, GEN7_SO_NUM_PRIMS_WRITTEN(0), idx);
} else {
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