Mesa (master): i965: Move post-sync non-zero flush for 3DSTATE_MULTISAMPLE.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 65b1f642ac2dff58498622bf6e0b7be8d9d3e20d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=65b1f642ac2dff58498622bf6e0b7be8d9d3e20d

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Thu Oct 24 00:38:27 2013 -0700

i965: Move post-sync non-zero flush for 3DSTATE_MULTISAMPLE.

For some reason, we put the flush in the caller, rather than just before
emitting the packet.  This is more than a cosmetic problem: BLORP calls
gen6_emit_3dstate_multisample() directly, and so it missed the flush.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Xinkai Chen <yeled.nova at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Cc: "9.2" <mesa-stable at lists.freedesktop.org>

---

 src/mesa/drivers/dri/i965/gen6_multisample_state.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_multisample_state.c b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
index c94c900..9f69ddc 100644
--- a/src/mesa/drivers/dri/i965/gen6_multisample_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_multisample_state.c
@@ -83,6 +83,9 @@ gen6_emit_3dstate_multisample(struct brw_context *brw,
       break;
    }
 
+   /* 3DSTATE_MULTISAMPLE is nonpipelined. */
+   intel_emit_post_sync_nonzero_flush(brw);
+
    int len = brw->gen >= 7 ? 4 : 3;
    BEGIN_BATCH(len);
    OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2));
@@ -138,9 +141,6 @@ static void upload_multisample_state(struct brw_context *brw)
       }
    }
 
-   /* 3DSTATE_MULTISAMPLE is nonpipelined. */
-   intel_emit_post_sync_nonzero_flush(brw);
-
    gen6_emit_3dstate_multisample(brw, num_samples);
    gen6_emit_3dstate_sample_mask(brw, num_samples, coverage,
          coverage_invert, sample_mask);