Mesa (master): i965: Also emit HiZ and Stencil packets when disabling depth on Gen6.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 5563dfabc8c1b7cc1a67e4d64311ea29aef43087
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5563dfabc8c1b7cc1a67e4d64311ea29aef43087

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Tue Aug 13 13:57:13 2013 -0700

i965: Also emit HiZ and Stencil packets when disabling depth on Gen6.

The normal drawing path does this, and it's necessary on Ivybridge,
so let's try it on Sandybridge too.  It's not explicitly documented
as necessary, but might help with hangs.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Tested-by: Xinkai Chen <yeled.nova at gmail.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Cc: "9.2" <mesa-stable at lists.freedesktop.org>

---

 src/mesa/drivers/dri/i965/gen6_blorp.cpp |   12 ++++++++++++
 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index ce215c2..8735270 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -930,6 +930,18 @@ gen6_blorp_emit_depth_disable(struct brw_context *brw,
    OUT_BATCH(0);
    OUT_BATCH(0);
    ADVANCE_BATCH();
+
+   BEGIN_BATCH(3);
+   OUT_BATCH(_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
+
+   BEGIN_BATCH(3);
+   OUT_BATCH(_3DSTATE_STENCIL_BUFFER << 16 | (3 - 2));
+   OUT_BATCH(0);
+   OUT_BATCH(0);
+   ADVANCE_BATCH();
 }