Mesa (master): nvc0: change logic for centering of eng2d blit when downsampling

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 47c19a5819444728b8662da4a0dbd5ca9af4698a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=47c19a5819444728b8662da4a0dbd5ca9af4698a

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Fri Apr 18 00:08:16 2014 -0400

nvc0: change logic for centering of eng2d blit when downsampling

We want to center the sample. The old code may have been correct given
the limited values of ms_x/y, but the new logic should be more
intuitive. Note that ms_x can only be 1/2 and ms_y can only be 0/1.

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/nvc0/nvc0_surface.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index 32d234e..ac37e0e 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -1066,8 +1066,8 @@ nvc0_blit_eng2d(struct nvc0_context *nvc0, const struct pipe_blit_info *info)
 
    if (src->base.base.nr_samples > dst->base.base.nr_samples) {
       /* center src coorinates for proper MS resolve filtering */
-      srcx += (int64_t)(src->ms_x + 0) << 32;
-      srcy += (int64_t)(src->ms_y + 1) << 31;
+      srcx += (int64_t)1 << (src->ms_x + 31);
+      srcy += (int64_t)1 << (src->ms_y + 31);
    }
 
    dstx = info->dst.box.x << dst->ms_x;