Mesa (master): nvc0/ir: offset appears to come before the Z ref

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: f782d6e792db2ed7773a2d22866dbcdb1e4062ee
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f782d6e792db2ed7773a2d22866dbcdb1e4062ee

Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sat Apr 26 20:29:47 2014 -0400

nvc0/ir: offset appears to come before the Z ref

Fixes textureGatherOffset when used with a shadow sampler. Also verified
against blob compiler with textureLodOffset manually (no piglit tests
for texture[Lod]Offset + shadow samplers).

Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp |    4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index dc1eb5e..0b439dd 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -737,10 +737,12 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
    assert(chipset >= NVISA_GK104_CHIPSET ||
           !i->tex.useOffsets || !i->tex.target.isMS());
 
-   // offset is last source (lod 1st, dc 2nd)
+   // offset is between lod and dc
    if (i->tex.useOffsets) {
       int n, c;
       int s = i->srcCount(0xff, true);
+      if (i->tex.target.isShadow())
+         s--;
       if (i->srcExists(s)) // move potential predicate out of the way
          i->moveSources(s, 1);
       if (i->tex.useOffsets == 4 && i->srcExists(s + 1))