Mesa (master): i965/vec4: Use MOV, not OR, to set URB write channel mask bits.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: af13cf609f4257768ad8b80be8cec7f2e6ca8c81
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=af13cf609f4257768ad8b80be8cec7f2e6ca8c81

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Sun Aug 10 20:06:44 2014 -0700

i965/vec4: Use MOV, not OR, to set URB write channel mask bits.

g0.5 has nothing of value to contribute to m0.5.  In both the VS and GS
payload, g0.5 contains the scratch space pointer - which is definitely
not of any use.  The GS payload also contains FFTID, but the URB write
message header doesn't want FFTID.

The only reason I used OR was because Eric originally requested it.
On Broadwell, I used MOV, and that's worked out fine.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>
Reviewed-by: Matt Turner <mattst88 at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c |    6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index a39746f..a1acd78 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2281,10 +2281,8 @@ void brw_urb_WRITE(struct brw_compile *p,
       brw_push_insn_state(p);
       brw_set_default_access_mode(p, BRW_ALIGN_1);
       brw_set_default_mask_control(p, BRW_MASK_DISABLE);
-      brw_OR(p, retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, msg_reg_nr, 5),
-		       BRW_REGISTER_TYPE_UD),
-	        retype(brw_vec1_grf(0, 5), BRW_REGISTER_TYPE_UD),
-		brw_imm_ud(0xff00));
+      brw_MOV(p, get_element_ud(brw_message_reg(msg_reg_nr), 5),
+                 brw_imm_ud(0xff00));
       brw_pop_insn_state(p);
    }