Mesa (master): i965: Emit 0.0:F sources with type VF instead.

[Matt Turner]

Module: Mesa
Branch: master
Commit: 99af02fb1778a425f1f3d211018d294b8d3b2245
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=99af02fb1778a425f1f3d211018d294b8d3b2245

Author: Matt Turner <mattst88 at gmail.com>
Date:   Fri May  2 14:47:55 2014 -0700

i965: Emit 0.0:F sources with type VF instead.

Number of compacted instructions: 817752 -> 827404 (1.18%)

Reviewed-by: Eric Anholt <eric at anholt.net>

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c |   16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index d8efa01..1810233 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -357,6 +357,22 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn,
       } else {
          insn->bits1.da1.src1_reg_type = BRW_HW_REG_TYPE_UD;
       }
+
+      /* Compacted instructions only have 12-bits (plus 1 for the other 20)
+       * for immediate values. Presumably the hardware engineers realized
+       * that the only useful floating-point value that could be represented
+       * in this format is 0.0, which can also be represented as a VF-typed
+       * immediate, so they gave us the previously mentioned mapping on IVB+.
+       *
+       * Strangely, we do have a mapping for imm:f in src1, so we don't need
+       * to do this there.
+       *
+       * If we see a 0.0:F, change the type to VF so that it can be compacted.
+       */
+      if (insn->bits3.ud == 0x0 &&
+          insn->bits1.da1.src0_reg_type == BRW_HW_REG_TYPE_F) {
+         insn->bits1.da1.src0_reg_type = BRW_HW_REG_IMM_TYPE_VF;
+      }
    }
    else
    {