Mesa (master): i965/fs: Don't use brw_imm_* unnecessarily.

[Matt Turner]

Module: Mesa
Branch: master
Commit: c938be8ad272a06bc0e91c4e718b61a0c5de400e
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c938be8ad272a06bc0e91c4e718b61a0c5de400e

Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu Apr 17 11:53:22 2014 -0700

i965/fs: Don't use brw_imm_* unnecessarily.

Using brw_imm_* creates a source with file=HW_REG, and the scheduler
inserts barrier dependencies when it sees HW_REG. None of these are
hardware-registers in the sense that they're special and scheduling
shouldn't touch them. A few of the modified cases already have HW_REGs
for other sources, so it won't allow extra flexibility in some cases.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_fs.cpp         |    4 ++--
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |    6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0116c4e..5605db3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1311,8 +1311,8 @@ fs_visitor::emit_sampleid_setup(ir_variable *ir)
        * These computations hold good for 4x multisampling as well.
        */
       emit(BRW_OPCODE_AND, t1,
-           fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
-           fs_reg(brw_imm_d(0xc0)));
+           fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD)),
+           fs_reg(0xc0));
       emit(BRW_OPCODE_SHR, t1, t1, fs_reg(5));
       /* This works for both SIMD8 and SIMD16 */
       emit(MOV(t2, brw_imm_v(0x3210)));
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index ff3d0f7..171f063 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1523,7 +1523,7 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
 	    fs_reg chan = coordinate;
 	    chan.reg_offset += i;
 
-	    inst = emit(BRW_OPCODE_SEL, chan, chan, brw_imm_f(0.0));
+	    inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
 	    inst->conditional_mod = BRW_CONDITIONAL_G;
 
 	    /* Our parameter comes in as 1.0/width or 1.0/height,
@@ -2386,7 +2386,7 @@ fs_visitor::emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
    unsigned mlen = 0;
 
    /* Initialize the sample mask in the message header. */
-   emit(MOV(brw_uvec_mrf(8, mlen, 0), brw_imm_ud(0)))
+   emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
       ->force_writemask_all = true;
 
    if (fp->UsesKill) {
@@ -2432,7 +2432,7 @@ fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
    unsigned mlen = 0;
 
    /* Initialize the sample mask in the message header. */
-   emit(MOV(brw_uvec_mrf(8, mlen, 0), brw_imm_ud(0)))
+   emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
       ->force_writemask_all = true;
 
    if (fp->UsesKill) {