Mesa (master): i965/fs: Use the correct base_mrf for spilling pairs in SIMD8

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 493bfa54a57e2feddd887ba0ec3d5ef139e82f3b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=493bfa54a57e2feddd887ba0ec3d5ef139e82f3b

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Thu Oct  2 16:04:57 2014 -0700

i965/fs: Use the correct base_mrf for spilling pairs in SIMD8

Before, we were hard-coding the base_mrf based on dispatch width not number
of registers spilled at a time.  This caused us to emit instructions with a
base_mrf or 14 and a mlen of 3 so we used the magical non-existant m16
register.  This fixes the problem.

Signed-off-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |    7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 176f91e..32669f6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -656,11 +656,12 @@ void
 fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src,
                        uint32_t spill_offset, int count)
 {
-   int spill_base_mrf = dispatch_width > 8 ? 13 : 14;
-
    int reg_size = 1;
-   if (count % 2 == 0)
+   int spill_base_mrf = 14;
+   if (count % 2 == 0) {
+      spill_base_mrf = 13;
       reg_size = 2;
+   }
 
    for (int i = 0; i < count / reg_size; i++) {
       fs_inst *spill_inst =