Mesa (master): i965/fs: Don't interfere with too many base registers

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 2ec161b2396b08341264965a5825152784b54549
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ec161b2396b08341264965a5825152784b54549

Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Mon Oct  6 21:27:06 2014 -0700

i965/fs: Don't interfere with too many base registers

On older GENs in SIMD16 mode, we were accidentally building too much
interference into our register classes.  Since everything is divided by 2,
the reigster allocator thinks we have 64 base registers instead of 128.
The actual GRF mapping still needs to be doubled, but as far as the ra_set
is concerned, we only have 64.  We were accidentally adding way too much
interference.

Signed-off-by: Jason Ekstrand <jason.ekstrand at gmail.com>
Reviewed-by: Matt Turner <mattst88 at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 34ee40f..0c4888f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -179,8 +179,8 @@ brw_alloc_reg_set(struct intel_screen *screen, int reg_width)
 
             ra_reg_to_grf[reg] = j * 2;
 
-            for (int base_reg = j * 2;
-                 base_reg < j * 2 + class_sizes[i];
+            for (int base_reg = j;
+                 base_reg < j + (class_sizes[i] + 1) / 2;
                  base_reg++) {
                ra_add_transitive_reg_conflict(regs, base_reg, reg);
             }