Mesa (master): i965/fs: Don't [un] spill multiple registers at a time in SIMD8 mode
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Mon Oct 27 20:36:29 UTC 2014
Module: Mesa
Branch: master
Commit: 76bb695f096667383597af78efd29dc466858dc6
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76bb695f096667383597af78efd29dc466858dc6
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date: Fri Oct 24 11:37:55 2014 -0700
i965/fs: Don't [un]spill multiple registers at a time in SIMD8 mode
I thought this would be a clever way to make spilling less expensive.
However, it appears that the oword read/write messages we are using for
spilling ignore the execution size and assume SIMD16 whenever working with
more than one register.
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 7ae6c75..ee5e123 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -688,8 +688,10 @@ fs_visitor::emit_unspill(bblock_t *block, fs_inst *inst, fs_reg dst,
uint32_t spill_offset, int count)
{
int reg_size = 1;
- if (count % 2 == 0)
+ if (dispatch_width == 16 && count % 2 == 0) {
reg_size = 2;
+ dst.width = 16;
+ }
for (int i = 0; i < count / reg_size; i++) {
/* The gen7 descriptor-based offset is 12 bits of HWORD units. */
@@ -722,7 +724,7 @@ fs_visitor::emit_spill(bblock_t *block, fs_inst *inst, fs_reg src,
{
int reg_size = 1;
int spill_base_mrf = 14;
- if (count % 2 == 0) {
+ if (dispatch_width == 16 && count % 2 == 0) {
spill_base_mrf = 13;
reg_size = 2;
}
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