Mesa (master): i965: Add field intel_mipmap_tree::disable_aux_buffers

[Chad Versace]

Module: Mesa
Branch: master
Commit: d3b042f359df5836d4a4f56664eb228fc80772c0
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3b042f359df5836d4a4f56664eb228fc80772c0

Author: Chad Versace <chad.versace at intel.com>
Date:   Mon Apr  6 06:46:09 2015 -0700

i965: Add field intel_mipmap_tree::disable_aux_buffers

The new field disables allocation of auxiliary buffers, such as the HiZ
buffer and MCS buffer. This is useful for sharing the miptree bo with an
external client that doesn't understand auxiliary buffers.

We need this field to safely render to a buffer that was imported with
EGL_EXT_image_dma_buf_import, because EGL does not yet have extensions
to manage flushing and invalidating auxiliary buffers.

Nothing yet enables this field. That's left to follow-up patches.

Testing:
  - Tested on Ivybridge Chromebook Pixel with WebGL Aquarium and
    YouTube.
  - No Piglit regressions on Broadwell with `piglit run -p gbm
    tests/quick.py`.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Tapani Pälli <tapani.palli at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |   24 ++++++++++++++++++++++--
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |    7 +++++++
 2 files changed, 29 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 492338b..ec0bb19 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -59,7 +59,8 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
  * created, based on the chip generation and the surface type.
  */
 static enum intel_msaa_layout
-compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target)
+compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target,
+                    bool disable_aux_buffers)
 {
    /* Prior to Gen7, all MSAA surfaces used IMS layout. */
    if (brw->gen < 7)
@@ -85,6 +86,11 @@ compute_msaa_layout(struct brw_context *brw, mesa_format format, GLenum target)
        */
       if (brw->gen == 7 && _mesa_get_format_datatype(format) == GL_INT) {
          return INTEL_MSAA_LAYOUT_UMS;
+      } else if (disable_aux_buffers) {
+         /* We can't use the CMS layout because it uses an aux buffer, the MCS
+          * buffer. So fallback to UMS, which is identical to CMS without the
+          * MCS. */
+         return INTEL_MSAA_LAYOUT_UMS;
       } else {
          return INTEL_MSAA_LAYOUT_CMS;
       }
@@ -176,6 +182,9 @@ intel_is_non_msrt_mcs_buffer_supported(struct brw_context *brw,
    if (brw->gen < 7)
       return false;
 
+   if (mt->disable_aux_buffers)
+      return false;
+
    /* MCS is only supported for color buffers */
    switch (_mesa_get_format_base_format(mt->format)) {
    case GL_DEPTH_COMPONENT:
@@ -276,6 +285,7 @@ intel_miptree_create_layout(struct brw_context *brw,
    mt->logical_height0 = height0;
    mt->logical_depth0 = depth0;
    mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_NO_MCS;
+   mt->disable_aux_buffers = false; /* hardcoded for now */
    exec_list_make_empty(&mt->hiz_map);
 
    /* The cpp is bytes per (1, blockheight)-sized block for compressed
@@ -293,7 +303,8 @@ intel_miptree_create_layout(struct brw_context *brw,
 
    if (num_samples > 1) {
       /* Adjust width/height/depth for MSAA */
-      mt->msaa_layout = compute_msaa_layout(brw, format, mt->target);
+      mt->msaa_layout = compute_msaa_layout(brw, format,
+                                            mt->target, mt->disable_aux_buffers);
       if (mt->msaa_layout == INTEL_MSAA_LAYOUT_IMS) {
          /* From the Ivybridge PRM, Volume 1, Part 1, page 108:
           * "If the surface is multisampled and it is a depth or stencil
@@ -440,6 +451,9 @@ intel_miptree_create_layout(struct brw_context *brw,
 
    brw_miptree_layout(brw, mt);
 
+   if (mt->disable_aux_buffers)
+      assert(mt->msaa_layout != INTEL_MSAA_LAYOUT_CMS);
+
    return mt;
 }
 
@@ -1313,6 +1327,7 @@ intel_miptree_alloc_mcs(struct brw_context *brw,
 {
    assert(brw->gen >= 7); /* MCS only used on Gen7+ */
    assert(mt->mcs_mt == NULL);
+   assert(!mt->disable_aux_buffers);
 
    /* Choose the correct format for the MCS buffer.  All that really matters
     * is that we allocate the right buffer size, since we'll always be
@@ -1379,6 +1394,7 @@ intel_miptree_alloc_non_msrt_mcs(struct brw_context *brw,
                                  struct intel_mipmap_tree *mt)
 {
    assert(mt->mcs_mt == NULL);
+   assert(!mt->disable_aux_buffers);
 
    /* The format of the MCS buffer is opaque to the driver; all that matters
     * is that we get its size and pitch right.  We'll pretend that the format
@@ -1692,6 +1708,9 @@ intel_miptree_wants_hiz_buffer(struct brw_context *brw,
    if (mt->hiz_buf != NULL)
       return false;
 
+   if (mt->disable_aux_buffers)
+      return false;
+
    switch (mt->format) {
    case MESA_FORMAT_Z_FLOAT32:
    case MESA_FORMAT_Z32_FLOAT_S8X24_UINT:
@@ -1709,6 +1728,7 @@ intel_miptree_alloc_hiz(struct brw_context *brw,
 			struct intel_mipmap_tree *mt)
 {
    assert(mt->hiz_buf == NULL);
+   assert(!mt->disable_aux_buffers);
 
    if (brw->gen == 7) {
       mt->hiz_buf = intel_gen7_hiz_buf_create(brw, mt);
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 0cb64d2..3dd37883 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -492,6 +492,13 @@ struct intel_mipmap_tree
     */
    uint32_t fast_clear_color_value;
 
+   /**
+    * Disable allocation of auxiliary buffers, such as the HiZ buffer and MCS
+    * buffer. This is useful for sharing the miptree bo with an external client
+    * that doesn't understand auxiliary buffers.
+    */
+   bool disable_aux_buffers;
+
    /* These are also refcounted:
     */
    GLuint refcount;