Mesa (master): 76 new commits
Jason Ekstrand
jekstrand at kemper.freedesktop.org
Mon Aug 3 16:42:13 UTC 2015
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=da1b1bf85cdc691ec27f379de84dec495cdd51e0
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 15 09:32:17 2015 +0200
i965/nir: Do not scalarize phis in non-scalar setups
Significantly reduces register pressure in some piglit tests.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34d162260f513a7eaec12611e3859bb34230cf33
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jul 8 16:08:17 2015 +0200
i965/vec4: Handle uniform and GRF array access on vertex programs (NIR)
When the NIR-vec4 pass is enabled, handles uniform and GRF array access
on ARB_vertex_program like it is done on vertex shaders.
When the old IR-vec4 pass is used, emit_program_code() emits pull constant
loads directly instead of using relative addressing, hence to call to
move_uniform_array_access_to_pull_constants() is not needed and it is enough
to call to split_uniform_registers().
The patch also calls to move_grf_array_access_to_scratch() like it is
done for shaders, however I suspect this is a no-op for vertex programs and
we could remove it.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=82f2e706bfd646b91bc0b8beecdff4e54b1f7b04
Author: Antia Puentes <apuentes at igalia.com>
Date: Mon Jun 29 14:21:38 2015 +0200
i965/nir/vec4: Handle uniforms on vertex programs
The implementation takes into account that on ARB_vertex_program
only a single nir variable is generated to support all the uniform data.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=90825e3ca977057c8f3d6ad2d1aa38277cc3ff11
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jul 8 12:44:15 2015 +0200
i965/vec4: Enable NIR-vec4 pass on ARB_vertex_programs
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=287b006a673dabe3e21cc207a1b4622ef91a877e
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 1 10:12:10 2015 +0200
i965/nir/gs: Implement support for gl_InvocationID system value
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7eced3aa863394c6e74ac3f037ed1cf9c481fe37
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Mon Jul 13 15:51:17 2015 +0200
i965/gs/gen6: Refactor ir_emit_vertex and ir_end_primitive for gen6
So the implementation is independent of GLSL IR and the visit methods of the
gen6 GS visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1836201fde1826c82f579fb132455c8df4176ecd
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 29 14:08:11 2015 +0200
i965/nir/gs: Implement EmitVertex and EndPrimitive
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=551af29d2d8be33b66641fe47ee5156489c16132
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 29 13:52:30 2015 +0200
i965/nir/gs: Handle geometry shaders inputs
Outputs from the vertex shader become array inputs in the geomtry shader,
but the arrays are interleaved, so we need to map our inputs accordingly.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ade42755f8900aaf67073214c073419f734e7a8
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Mon Jun 29 13:37:31 2015 +0200
i965/gs: Refactor ir_emit_vertex and ir_end_primitive
So the implementation is independent of GLSL IR and the visit methods of the
vec4 visitor. This way we will be able to reuse that implementation directly
from the NIR vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=38fc4a91cd5c04fdd5921b8776f8e203513ab517
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Wed Jul 1 09:51:25 2015 +0200
i965/nir: Enable NIR-vec4 pass on geometry shaders
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=418c004f802e63ca4e9f3456a46498d2fc543854
Author: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Date: Thu Jun 11 12:32:26 2015 +0200
nir: Fix output swizzle in get_mul_for_src
Avoid copying an overwritten swizzle, use the original values.
Example:
Former swizzle[] = xyzw
src->swizzle[] = zyxx
The expected output swizzle = zyxx but if we reuse swizzle in the loop,
then output swizzle would be zyzz.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19cf934f7f18237e1a212b0a019026d5d36c6fac
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Jul 6 15:08:15 2015 +0200
i965/nir/vec4: Add implementation of nir_emit_texture()
Uses the nir structure to get all the info needed (sources,
dest reg, etc), and then it uses the common
vec4_visitor::emit_texture to emit the final code.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1343f403b2d08a0877f17133abb6dccf0f51127b
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Jul 6 14:33:21 2015 +0200
i965/ir/vec4: Refactor visit(ir_texture *ir)
Splitted in two. The emission is moved to a new vec4_visitor
method, vec4_visitor::emit_texture, ir order to be reused
on the nir path.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d43d27df742ad95a086580bae2ee08a0bc00e69
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Sat May 23 23:42:58 2015 +0200
i965/vec4: Add a new dst_reg constructor accepting a brw_reg_type
This is useful for the upcoming texture support in NIR->vec4 pass,
as we found several cases where the brw_type is available, but not
the glsl_type.
Without this new constructor, the alternative would be:
dst_reg reg(MRF, <reg>)
reg.type = <brw_type>
reg.writemask = <mask>
Adding a new constructor makes code easier to read.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c15eea2afa7a295992cde949b8e2a5d4552f6290
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Mon Jul 6 13:31:05 2015 +0200
i965/vec4: Change vec4_visitor::swizzle_result() method to allow reuse
This patch changes the signature of swizzle_result() to accept lower
level arguments. The purpose is to reuse it in the upcoming NIR->vec4
pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=57182332b84b58fed6641314def67450893b7419
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Jun 18 12:12:21 2015 +0200
i965/vec4: Change vec4_visitor::gather_channel() method to allow reuse
This patch changes the signature of gather_channel() to accept the gather
component directly instead of fetching it internally from ir_texture.
This will allow reuse in the upcoming NIR->vec4 pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=72c8d7721feb966cf8530a3ee2642f0b842dc0f8
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Jun 18 11:31:54 2015 +0200
i965/vec4: Change vec4_visitor::emit_mcs_fetch() method to allow reuse
This patch changes the signature of emit_mcs_fetch() to accept lower level
arguments. The purpose is to reuse it in the upcoming NIR->vec4 pass.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=434481f3155040217c3e5a8da98dab4248435f0e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Thu Jun 18 09:37:33 2015 +0200
i965/vec4: Move is_high_sample() method to vec4_visitor class
The is_high_sample() method is currently accessible only in the implementation of
vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass, lets make
it a method of the class instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db8a6de571bb72ef43209a415e5492001a87b1d8
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jun 17 10:59:10 2015 +0200
i965/nir: Add new utility method brw_glsl_base_type_for_nir_type()
This method returns the glsl_base_type corresponding to a nir_alu_type.
It will factorize code currently present in fs_nir, that can be reused
in vec4_nir on its upcoming emit_texture support.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=583c1c61703826002ba0f202e8ef7bc2c822ef1d
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jun 17 10:20:19 2015 +0200
i965/nir/vec4: Implement nir_emit_jump
This implementation is taken as-is from fs_nir.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b4a6fa4c09d36e0e5c00309e6ea37300ea38f78
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:10:44 2015 +0200
i965/nir/vec4: Mark as unreachable ops that should be already lowered
NIR ALU operations:
* nir_op_fabs
* nir_op_iabs
* nir_op_fneg
* nir_op_ineg
* nir_op_fsat
should be lowered by lower_source mods
* nir_op_fdiv
should be lowered in the compiler by DIV_TO_MUL_RCP.
* nir_op_fmod
should be lowered in the compiler by MOD_TO_FLOOR.
* nir_op_fsub
* nir_op_isub
should be handled by ir_sub_to_add_neg.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16072834babc487f78472f7e7b59d35249a3aac8
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:08:27 2015 +0200
i965/nir/vec4: Implement vector "any" operation
Adds NIR ALU operations:
* nir_op_bany2
* nir_op_bany3
* nir_op_bany4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa4e3c3c9f6f3a72a032499fccaa6e222d6a7fa4
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:06:44 2015 +0200
i965/nir/vec4: Implement the dot product operation
Adds NIR ALU operations:
* nir_op_fdot2
* nir_op_fdot3
* nir_op_fdot4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96106e2a9f214d98fc2e99c65398f95d41a3b879
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:05:29 2015 +0200
i965/nir/vec4: Implement conditional select
Adds NIR ALU operations:
* nir_op_bcsel
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b38fcd0aea8d17919ecd9cc7afc518cfb2c01c27
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:52:43 2015 +0200
i965/nir/vec4: Implement linear interpolation
Adds NIR ALU operation:
* nir_op_flrp
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=314474872b77f291132a01f7c1df2788586fc943
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 10:01:07 2015 +0200
i965/vec4: Return the emitted instruction in emit_lrp()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b64bd1fdc37eed1bb62d2b32ad22f0f77501f7f2
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:51:10 2015 +0200
i965/nir/vec4: Implement floating-point fused multiply-add
Adds NIR ALU operation:
* nir_op_ffma
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d12e165dbb403c3cf86ab7f1b8f28ab6188b479f
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:49:31 2015 +0200
i965/nir/vec4: Implement "shift" operations
Adds NIR ALU operations:
* nir_op_ishl
* nir_op_ishr
* nir_op_ushr
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=798cb33a256f703ecaf56d4443e12055484d4bcc
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:47:41 2015 +0200
i965/nir/vec4: Implement the "sign" operation
Follows the vec4_visitor IR implementation but
sets the saturate value in addition.
Adds NIR ALU operations:
* nir_op_fsign
* nir_op_isign
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e1e6facbf828258a9a8ca09da846d1baa21d984
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:44:25 2015 +0200
i965/nir/vec4: Implement bit operations
Same implementation than the IR case.
Adds NIR ALU operations:
* nir_op_bitfield_reverse
* nir_op_bit_count
* nir_op_ufind_msb
* nir_op_ifind_msb
* nir_op_find_lsb
* nir_op_ubitfield_extract
* nir_op_ibitfield_extract
* nir_op_bfm
* nir_op_bfi
* nir_op_bitfield_insert
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e874985ce50d902535e1eb766bd252c921b5d8f
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:29:04 2015 +0200
i965/nir/vec4: Implement pack/unpack operations
* Lowered floating-point pack and unpack operations are not valid in VS.
* Pack and unpack 2x16 operations should be handled by lower_packing_builtins.
* Adds NIR ALU operations:
* nir_op_pack_half_2x16
* nir_op_unpack_half_2x16
* nir_op_unpack_unorm_4x8
* nir_op_unpack_snorm_4x8
* nir_op_pack_unorm_4x8
* nir_op_pack_snorm_4x8
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f10c2f3d73ae41ff83afcdbe225121b8336f499
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:23:10 2015 +0200
i965/nir/vec4: "noise" ops should already be lowered
Marked them as unreachable.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa4731f4a53aa21e53a62f42f3afdc19b0ce4c8e
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:21:30 2015 +0200
i965/nir/vec4: Implement "bool<->int,float" format conversion
Used the same implementation than the vec4_visitor NIR.
Adds NIR ALU operations:
* nir_op_b2i
* nir_op_b2f
* nir_op_f2b
* nir_op_i2b
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f14199a8fb802f6672d559fa958a5ee84e3e13f1
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:07:20 2015 +0200
i965/nir/vec4: Implement logical operators
Adds NIR ALU operations:
* nir_op_inot
* nir_op_ixor
* nir_op_ior
* nir_op_iand
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51aeafaf96b3b349e007ad05738bc1e05663fedf
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 09:01:28 2015 +0200
i965/nir/vec4: Implement non-equality ops on vectors
Adds NIR ALU operations:
* nir_op_bany_fnequal2
* nir_op_bany_inequal2
* nir_op_bany_fnequal3
* nir_op_bany_inequal3
* nir_op_bany_fnequal4
* nir_op_bany_inequal4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8be4b876c90192c3a5e6fcc9b526f43a3f7bfc11
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:55:24 2015 +0200
i965/nir/vec4: Implement equality ops on vectors
Adds NIR ALU operations:
* nir_op_ball_fequal2
* nir_op_ball_iequal2
* nir_op_ball_fequal3
* nir_op_ball_iequal3
* nir_op_ball_fequal4
* nir_op_ball_iequal4
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84d4a9dc2ca3d98f19cc9125a5ff1ac1225f360d
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:49:42 2015 +0200
i965/nir/vec4: Implement non-vector comparison ops
Adds NIR ALU operations:
* nir_op_flt
* nir_op_ilt
* nir_op_ult
* nir_op_fge
* nir_op_ige
* nir_op_uge
* nir_op_feq
* nir_op_ieq
* nir_op_fne
* nir_op_ine
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9c41affcf67f30d7f6c74c17ea34bc42756d56d
Author: Antia Puentes <apuentes at igalia.com>
Date: Fri Apr 17 17:58:35 2015 +0200
i965/nir: Add utility method for comparisons
This method returns the brw_conditional_mod value used when emitting
comparative ALU operations.
It could be moved to brw_nir in the future to reuse it in fs_nir backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dae6025e8efdfb759458a3243c8cd1588f485135
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Apr 14 12:04:24 2015 +0200
i965/nir/vec4: Derivatives are not allowed in VS
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e6f1c38a591fa39cff1c32a2cfdda927145756a
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:34:57 2015 +0200
i965/nir/vec4: Implement min/max operations
Adds NIR ALU operations:
* nir_op_fmin
* nir_op_imin
* nir_op_umin
* nir_op_fmax
* nir_op_imax
* nir_op_umax
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d53098393e3929b0c8d82f56144c7497b184f5b7
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:32:58 2015 +0200
i965/vec4: Return the emitted instruction in emit_minmax()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7553a51a68c0b2030265fe741f9c511b65047914
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:25:02 2015 +0200
i965/nir/vec4: Implement various rounding functions
Adds NIR ALU operations:
* nir_op_ftrunc
* nir_op_fceil
* nir_op_ffloor
* nir_op_ffrac
* nir_op_fround_even
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ce159ec7fbcdf00c488b77f63e565e89ef6cab5
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:22:14 2015 +0200
i965/nir/vec4: Implement carry/borrow for addition/subtraction
Adds NIR ALU operations:
* nir_op_uadd_carry
* nir_op_usub_borrow
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=62cef7b0723ad6ca49ed06a6899a5852e41359e8
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:10:18 2015 +0200
i965/nir/vec4: Implement more math operations
Adds NIR ALU operations:
* nir_op_frcp
* nir_op_fexp2
* nir_op_flog2
* nir_op_fexp
* nir_op_flog
* nir_op_fsin
* nir_op_fcos
* nir_op_idiv
* nir_op_udiv
* nir_op_umod
* nir_op_ldexp
* nir_op_fsqrt
* nir_op_frsq
* nir_op_fpow
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=068a41b349e8bc30293c44d96553184f7562949f
Author: Antia Puentes <apuentes at igalia.com>
Date: Wed Jun 17 00:04:09 2015 +0200
i965/vec4: Return the last emitted instruction in emit_math()
Needed in the NIR backend to set the "saturate" value of the
instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9acebf146184c35e6897b91fff414c5295d47996
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 23:50:46 2015 +0200
i965/nir/vec4: Implement multiplication
Implementation based on the vec4_visitor IR implementation
for the operations ir_binop_mul and ir_binop_imul_high.
Adds NIR ALU operations:
* nir_op_fmul
* nir_op_imul
* nir_op_imul_high
* nir_op_umul_high
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0675842b56a956befbac4a3b912823e73a95a500
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 23:48:46 2015 +0200
i965/nir/vec4: Implement the addition operation
Adds NIR ALU operations:
* nir_op_fadd
* nir_op_iadd
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f39b547da4f9949d1b1f9f0df07d08951f0358d
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 23:04:32 2015 +0200
i965/nir/vec4: Implement int<->float format conversion ops
Adds NIR ALU operations:
* nir_op_f2i
* nir_op_f2u
* nir_op_i2f
* nir_op_u2f
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4f02f47e70d384531ac68e6d33a62fdcdbd1f28
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:58:15 2015 +0200
i965/nir/vec4: Lower "vecN" instructions and mark them unreachable
This enables NIR pass "lower_vec_to_movs" on shaders that work on vec4.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=79154d99d6e760b1daf327b4594dded18f1d4191
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:52:29 2015 +0200
i965/nir/vec4: Implement single-element "mov" operations
Adds NIR ALU operations:
* nir_op_imov
* nir_op_fmov
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e5d827f455f3c72af6cb8d60b97890bab8d5ad0
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Thu Jun 25 09:52:35 2015 +0200
i965/nir: Disable alu_to_scalar pass on non-scalar shaders
Disables nir_lower_alu_to_scalar when the shader stage being processed work
on vec4 vectors, like the upcoming NIR->vec4 backend.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef1b30ae637e613b384541324c199d2dbe6b44bd
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:30:16 2015 +0200
i965/nir/vec4: Prepare source and destination registers for ALU operations
This patch resolves and initializes the destination and the source
registers that are common to most ALU operations.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=168bbfa6ff22a586ad6307c187cfa3b8fff5f227
Author: Antia Puentes <apuentes at igalia.com>
Date: Tue Jun 16 22:10:32 2015 +0200
i965/nir/vec4: Implement loading values from an UBO
Based on the vec4_visitor IR implementation for the ir_binop_load_ubo
operation. Notice that unlike the vec4_visitor IR, adding the !=0
comparison for UBO bools is not needed here because that comparison is
already added by the nir_visitor when processing the ir_binop_load_ubo
(in UBOs "true" is any value different from zero, but for us is ~0).
Adds NIR instrinsics:
* nir_intrinsic_load_ubo_indirect
* nir_intrinsic_load_ubo
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=98d07022f5312967bdfd54069869c8d6c65117a7
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 22:03:17 2015 +0200
i965/nir/vec4: Implement atomic counter intrinsics (read, inc and dec)
The implementation is based on its fs_nir counterpart.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6cafb5dfdef8d8d25ee1e3375304cf35897d1f7
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jun 16 21:55:14 2015 +0200
i965/nir/vec4: Implement load_uniform intrinsic
For the indirect case we need to take the index delivered by
NIR and compute the parent uniform that we are accessing (the one
that we uploaded to a surface) and the constant offset into that
surface.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e76e8caecd30799500357a45468329f033a93932
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 21:36:49 2015 +0200
i965/nir/vec4: Implement intrinsics that load system values
These include:
nir_intrinsic_load_vertex_id_zero_base
nir_intrinsic_load_base_vertex
nir_intrinsic_load_instance_id
The source register is fetched from the nir_system_values map initialized
during nir_setup_system_values stage.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=662c4c99065381b8e265310d176cfdef6698ca57
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 21:31:49 2015 +0200
i965/nir/vec4: Implement store_output intrinsic
This implementation is based on the current URB setup in vec4_visitor, which
requires the output register to be stored in the output_reg array at variable's
original shader location index. But since nir_lower_io() pass uses the value
in var->data.driver_location, we need to put there var->data.location instead,
prior to calling nir_lower_io(), so that we end up with the correct index
in const_index[0].
The driver_location is not used at all, so this patch also disables the
nir_assign_var_locations pass on non-scalar shaders.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11ed02e1c81a2aa71b22b1d6847f58e41fd89271
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jul 21 20:21:21 2015 +0200
i965/vec4: Make sure that register types always match during emit_urb_slot()
Instead of relying on backends (currently vec4_visitor and soon NIR-vec4) to
store registers in output_reg with the correct type, this patch makes sure
that the common code in emit_urb_slot() always emit MOVs from output registers
using the same type on source and destination.
Since the actual type is not important, only that they match, we default to
float.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=167cb9663adc8c7c61807e503f66e85f955e7d5f
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 21:24:21 2015 +0200
i965/nir/vec4: Implement load_input intrinsic
The source register is fetched from the nir_inputs map built during
nir_setup_inputs stage.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=afe085a0ca01f659c69456018e5f5076c9dde47d
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 20:25:55 2015 +0200
i965/nir/vec4: Implement loop statements (nir_cf_node_loop)
This is taken as-is from fs_nir.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c0436dbf87fef76ba67456f215d9285c38f1816
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jun 16 20:16:15 2015 +0200
i965/nir/vec4: Implement conditional statements (nir_cf_node_if)
The same we do in the FS NIR backend, only that here we need to consider
the number of components in the condition and adjust the swizzle
accordingly.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3187ea31ede6bc181ee561573d127aa2e485657
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 17:43:02 2015 +0200
i965/nir/vec4: Add get_nir_dst() and get_nir_src() methods
These methods are essential for the implementation of the NIR->vec4 pass. They
work similar to their fs_nir counter-parts.
When processing instructions, these methods are invoked to resolve the
brw registers (source or destination) corresponding to the NIR sources
or destination. It uses the map of NIR register index to brw register for
all registers locally allocated in a block.
Signed-off-by: Samuel Iglesias Gonsalvez <siglesias at igalia.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97e205fd35bf77fd761caf24c611ff72cc0d85e2
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Fri Apr 17 18:10:50 2015 +0200
i965/nir: Move brw_type_for_nir_type() to brw_nir to allow reuse
Upcoming NIR->vec4 pass can benefit from this method, so lets move it up.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7152525374015594e037fa11bb64e1c7174829b
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 1 16:10:49 2015 +0200
i965/nir/vec4: Implement load_const intrinsic
Similar to fs_nir backend, a nir_local_values map will be filled with
newly allocated registers as the load_const instrinsic instructions are
processed. Later, get_nir_src() will fetch the registers from this map
for sources that are ssa.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5a3287f7392356386aa305c791d94b6d5dde6cc
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 20:53:28 2015 +0200
i965/vec4: Add auxiliary func to build a writemask from a component size
New method brw_writemask_for_size() will return a writemask with the first
'size' components activated.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e58fc56a5a396020cd299db11895120ec3da520
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Fri Jul 3 08:23:33 2015 +0200
i965/nir: Dot not assign direct uniform locations first for vec4-based shaders
In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we
need to implement nir_intrinsic_load_uniform. Otherwise we would need a
mapping to match the output of nir_lower_io to the actual uniform registers
we need to use.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01f6235020f9f0c2bc1a6e6ea9bd15c22fb2bcf5
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Thu Jun 18 13:52:21 2015 +0200
nir/nir_lower_io: Add vec4 support
The current implementation operates in scalar mode only, so add a vec4
mode where types are padded to vec4 sizes.
This will be useful in the i965 driver for its vec4 nir backend
(and possbly other drivers that have vec4-based shaders).
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e839727ed2378a01d3b657bad83abd4728e8da6
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 22 09:35:28 2015 +0200
i965/nir: Pass a is_scalar boolean to brw_create_nir()
The upcoming introduction of NIR->vec4 pass will require that some NIR
lowering passes are enabled/disabled depending on the type of shader
(scalar vs. vector).
With this patch we pass a 'is_scalar' variable to the process of
constructing the NIR, to let an external context decide how the shader
should be handled.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59006d3ad3ed5d29e84afa5931f425344e2ef658
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Wed Jul 22 09:34:35 2015 +0200
i965/nir/vec4: Add shader function implementation
It basically allocates registers local to a function in a nir_locals map,
then emits all its control-flow blocks.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4023b55fdd7005a8a100637c229a1c40648cdd2b
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 17:08:04 2015 +0200
i965/nir/vec4: Add setup for system values
Similar to other variable setups, system values will initialize the
corresponding register inside a 'nir_system_values' map, which will then
be queried later when processing the different system value intrinsics
for the appropriate register.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01c5617c8edc2f392363e9f8861d62a9fc9aa973
Author: Alejandro Piñeiro <apinheiro at igalia.com>
Date: Tue Jun 16 17:01:29 2015 +0200
i965/vec4: Redefine make_reg_for_system_value() to allow reuse in NIR->vec4 pass
The new virtual method is more flexible, it has a signature:
dst_reg *make_reg_for_system_value(int location, const glsl_type *type);
v2 (Jason Ekstrand):
Use the new version in unit tests so make check passes again
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=195156e571e851273c135847f91ed73b3bfc1914
Author: Iago Toral Quiroga <itoral at igalia.com>
Date: Tue Jun 16 14:30:31 2015 +0200
i965/nir/vec4: Add setup of uniform variables
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b929acb6a8659fdc06623b766bdf59904d8a3558
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 13:50:43 2015 +0200
i965/nir/vec4: Add setup of input variables in NIR->vec4 pass
This implementation sets up a map of input variable offsets to source registers
that are already initialized with the corresponding register offset.
This map will then be queried when processing load_input intrinsic operations,
to obtain the correct register source from which the input data will be loaded.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78e7ce2b7329f8cc3f771afbf39d3fa662e02d9e
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 13:39:48 2015 +0200
i965/vec4: Move type_size() method to brw_vec4_visitor class
The type_size() method is currently accessible only in the implementation
of vec4_visitor. Since we need to reuse it in the upcoming NIR->vec4 pass,
lets make it a method of the class instead.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47d68908f2c3ad3e9011a2cf910b04cd3300673a
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 12:26:39 2015 +0200
i965/nir/vec4: Select between new nir_vec4 or current vec4_visitor code-paths
The NIR->vec4 pass will be activated if both the following conditions are met:
* INTEL_USE_NIR environment variable is defined and is positive (1 or true)
* The stage is vertex shader (support for geometry shaders and
ARB_vertex_program will be added later).
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=abf4fa3c03ebe5716c90c8a310945c3621cf598f
Author: Eduardo Lima Mitev <elima at igalia.com>
Date: Tue Jun 16 12:08:09 2015 +0200
i965/nir/vec4: Add implementation placeholders for a new NIR->vec4 pass
This patch will add a brw_vec4_nir.cpp file filled with entry point methods to
the main functionality, following a structure similar to brw_fs_nir.cpp.
Subsequent patches in this series will be adding the implementations for these
methods, incrementally.
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
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