Mesa (master): 23 new commits

Tue Aug 11 12:09:19 UTC 2015

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c04a90e91a64a4a09d77c76c6ddcaca949e9b0e
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri May 1 17:00:02 2015 +0300

    docs: Mark ARB_shader_image_load_store as done on i965.

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=d03c65793a5ee31f1138cbd0fba6fac6cd942428
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu May 7 18:56:01 2015 +0300

    i965: Expose ARB_shader_image_load_store.
    
    Reviewed-by: Paul Berry <stereotype441 at gmail.com>
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=13a04abc277089275217dce119e18acf4d4ce52d
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Jul 27 14:33:06 2015 +0300

    i965/fs: Clamp image array indices to the array bounds on IVB.
    
    This fixes the spec at arb_shader_image_load_store@invalid index bounds
    piglit tests on IVB, which were causing a GPU hang and then a crash
    due to the invalid binding table index result of the array index
    calculation.  Other generations seem to behave sensibly when an
    invalid surface is provided so it doesn't look like we need to care.
    
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Reviewed-by: Chris Forbes <chrisf at ijw.co.nz>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a47ae8de2cf30fbe45318a18a2ea032f30ab7d10
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Jul 27 16:26:52 2015 +0300

    i965/fs: Translate image load, store and atomic NIR intrinsics.
    
    v2: Move array coordinate workaround into the surface builder.
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=912ef52c29fdc373889594b963cc93c89fa9e3f7
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sun Jun 28 21:16:31 2015 +0300

    i965/fs: Handle image uniforms in NIR programs.
    
    v2: Move the image_params array back to brw_stage_prog_data.
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4af27145fe2fec6586ce95e80a76cdcbfe933db1
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue May 5 21:07:15 2015 +0300

    i965: Implement logic to set up and upload an image uniform.
    
    v2: Move the image_params array back to brw_stage_prog_data.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=84431c1f1d343c85f3b7fa265293a1d245ba9cf3
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue May 5 21:05:45 2015 +0300

    i965: Teach type_size() about the size of an image uniform.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=caae52561dabb2d20f2369c547e660d078974285
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Jul 30 15:46:40 2015 +0300

    i965/fs: Implement image load, store and atomic.
    
    v2: Drop VEC4 suport.
    v3: Rebase.
    v4: Move array coordinate workaround into the surface builder.
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e8be000101cc6fe3846745b559f2d785430e253
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Jul 30 15:51:58 2015 +0300

    i965/fs: Import image format conversion primitives.
    
    Define bitfield packing, unpacking and type conversion operations in
    terms of which the image format conversion code will be implemented.
    These don't directly know about image formats: The packing and
    unpacking functions take a 4-tuple of bit shifts and a 4-tuple of bit
    widths as arguments, determining the bitfield position of each
    component.  Most of the remaining functions perform integer, fixed
    point normalized, and floating point type conversions, mapping between
    a target type with per-component bit widths given by a parameter and a
    matching native representation of the same type.
    
    v2: Drop VEC4 suport.
    v3: Rebase.
    v4: Fix clamping of negative floats in the unsigned case of
        emit_convert_to_scaled().
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=26ca81ce3029cbd2531f52635258aecae19bf185
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Wed Apr 22 16:45:28 2015 +0300

    i965/fs: Import image format metadata queries.
    
    Define some utility functions to query the bitfield layout of a given
    image format and whether it satisfies a number of more or less
    hardware-specific properties.
    
    v2: Drop VEC4 suport.
    v3: Add SKL support.
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=86dbd8af40deaa99aedf011e863b908173e63012
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Thu Jul 23 19:32:08 2015 +0300

    i965/fs: Import code to transform image coordinates into surface coordinates.
    
    Accounting for the padding required for 1D arrays in certain cases.
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a37619763a99b78aa574aca0058eda86de7a0dc
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Wed Apr 22 16:44:18 2015 +0300

    i965/fs: Import image memory offset calculation code.
    
    Define a function to calculate the memory address of the image
    location given by a vector of coordinates.  This is required in cases
    where we need to fall back to untyped surface access, which take a raw
    memory offset and know nothing about surface coordinates, type
    conversion or memory tiling and swizzling.  They are still useful
    because typed surface reads don't support any 64 or 128-bit formats on
    IVB, and they don't support any 128-bit formats on HSW and BDW.
    
    The tiling algorithm is implemented based on a number of parameters
    which are passed in as uniforms and determine whether the surface
    layout is X-tiled, Y-tiled or untiled.  This allows binding surfaces
    of different tiling layouts to the pipeline without recompiling the
    program.
    
    v2: Drop VEC4 suport.
    v3: Rebase.
    v4: Add plenty of comments (Jason).
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb19df7a626d02cb54614d4610af2d14720a2ef3
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Wed Apr 22 16:43:51 2015 +0300

    i965/fs: Import image access validity checks.
    
    These utility functions check whether an image access is valid.
    According to the spec an invalid image access should have no effect on
    the image and yield well-defined results.  Typically the hardware
    implements correct bounds and surface checking by itself, but in some
    cases (typed atomics on IVB and untyped messages elsewhere) we need to
    implement it in software to work around lacking hardware support.
    
    v2: Drop VEC4 suport.
    v3: Rebase.
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3569742ec458c0a881857d9deb782c1e11f195d8
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Nov 22 16:00:33 2013 -0800

    i965: Define implementation constants for ARB_shader_image_load_store.
    
    Reviewed-by: Paul Berry <stereotype441 at gmail.com>
    
    v2: Drop VS support pre-Gen8, drop GS support.
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=786e0853bebc3c4ab073bdbb48eec8ba5ea93842
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Feb 9 21:04:53 2015 +0200

    i965/gen7-8: Set up early depth/stencil control appropriately for image load/store.
    
    v2: Store early fragment test mode in brw_wm_prog_data instead of
        getting it from core mesa data structures (Ken).
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac7664e493655e290783c23a0412b9c70936da50
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Jul 13 14:21:07 2015 +0300

    i965/gen7-8: Poke the 3DSTATE UAV access enable bits.
    
    v2: Set the PS UAV-only bit on HSW (Ken).
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=acb6d90dc809283d9839685852f19f6b301b23d3
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue Feb 3 17:14:10 2015 +0200

    i965/gen7: Enable fragment shader dispatch if the program has image uniforms.
    
    Shaders with image uniforms may have side effects.  Make sure that
    fragment shader threads are dispatched if the shader has any image
    uniforms.
    
    v2: Use brw_stage_prog_data::nr_image_params to find out if the shader
        has image uniforms instead of checking core mesa data structures
        (Ken).
    
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=47f9b07e4cf79a8249c6f9f09148a6a0b4fabacc
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Jul 20 17:13:17 2015 +0300

    i965: Hook up image state upload.
    
    v2: Add CS support.  Move the image_params array back to
        brw_stage_prog_data.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Acked-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=868f1ba0a4e6e3057be5b8c2458db4773cf82034
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Mon Jul 13 17:19:29 2015 +0300

    i965: Reserve enough parameter entries for all image uniforms used in the program.
    
    v2: Add CS support.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=87a3e02d9bec689e110f820bba7b125b3e801fdd
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Wed Jan 21 17:34:49 2015 +0200

    i965: Define and initialize image parameter structure.
    
    This will be used to pass image meta-data to the shader when we cannot
    use typed surface reads and writes.  All entries except surface_idx
    and size are otherwise unused and will get eliminated by the uniform
    packing pass.  size will be used for bounds checking with some image
    formats and will be useful for ARB_shader_image_size too.  surface_idx
    is always used.
    
    v2: Add CS support.  Move the image_params array back to
        brw_stage_prog_data.
    v3: Improve documentation.
    
    Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3144844f5ca89cd5743bc9b0ac142ccf862af557
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Sat May 2 16:58:24 2015 +0300

    i965: Implement surface state set-up for shader images.
    
    v2: Add SKL support.
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cdb24a7c2238843d23b468275d479553f537e7e
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue May 12 15:56:54 2015 +0300

    i965: Fix brw_memory_barrier() for SKL.
    
    This works as-is on SKL, only the assertion needs to be relaxed.
    
    Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9094691378722304dd94deb76ad013bd65c7a5b
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Tue May 12 16:10:07 2015 +0300

    i965: Add SKL support to brw_miptree_get_horizontal_slice_pitch().
    
    Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>