Mesa (master): 43 new commits
Marek Olšák
mareko at kemper.freedesktop.org
Fri Aug 14 13:37:13 UTC 2015
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a90aa54fde37cbdf162bf909a9e895b764eb41ea
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Aug 13 23:46:13 2015 +0200
docs/relnotes: document amdgpu, GL 4.1 and other new features
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bfb9ee5ee0551ef2c2056e7fe2e63e35c629e3c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 22:59:41 2015 +0200
radeonsi: add all new VI PCI IDs including Fiji
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f47c59322e614d6304091207fc81cfa5beba6ea9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 16:23:53 2015 +0200
radeonsi: revert a wrong DB bug workaround for VI
The bug was misunderstood. Besides that, the bug affects a DB feature we
don't use yet.
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=839bf82606ae9c7b1c7d8d5055ab5e3cadae9bf9
Author: Boyuan Zhang <boyuan.zhang at amd.com>
Date: Wed Jul 8 16:54:48 2015 -0400
radeon/uvd: implement HEVC support
add context buffer to fix H265 uvd decode issue.
fix H265 corruption issue caused by incorrect assigned ref_pic_list.
v2: disable interlace for HEVC
add CZ sps flag workaround
fix coding style
Signed-off-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0654a9ca17c17fe140f70d126c878a0ce4736b76
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jul 13 13:36:27 2015 -0400
radeon/vce: disable VCE dual instance for harvest part
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=09def7e1e06827ab1eae091f0e765d91c6715cf9
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 10:14:14 2015 -0400
radeon/vce: implement VCE dual instance support
VCE dual instances are encoding in parallel, it needs two frames for
encoding with their own parameters in one IB. Master instance will check
the task info to find another frame, assign it to the slave instance
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4dfcf6e3a91be97fcf9d3f44e76a7a389f8f40b2
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 12:12:12 2015 -0400
radeon/video: config encode stacked frame number based on HW
since VCE 3.0 with dual instances, we need stack frames for them.
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=42bc4e6be434b398d9edaff0ed10dfb5bf89b6a6
Author: Christian König <christian.koenig at amd.com>
Date: Mon Jun 15 20:19:48 2015 +0200
radeon/vce: make reloc offset signed
We need a negative offset for FW 50.
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=57fabe9f3a21a2a370284575833637d37e987cb5
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jun 1 13:48:24 2015 -0400
radeon/vce: add config task and put task info into encoder v2
The config task has own task ID, extract the configuration functions
into config task.
v2 (chk): calculate offset automatically
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e91a67abfa5112acd481ee4a3f07c03f6ff2708c
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jun 15 15:20:20 2015 -0400
radeon/vce: fix VCE fail after rebase
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa80c1fe20f1fc33864f04fd9cf49f8bddfa4448
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jun 15 14:11:57 2015 -0400
radeon/vce: add dual pipe support for VI
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=468fcdcb4fafeba466bb1006ece1f16cc38805c7
Author: Leo Liu <leo.liu at amd.com>
Date: Fri May 29 13:43:00 2015 -0400
radeon/vce: add new firmware support for VI and CI
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1550790b3fab901c697e9d8e5b01ea67d8843e99
Author: Leo Liu <leo.liu at amd.com>
Date: Wed Apr 15 12:36:32 2015 -0400
radeon/vce: implement VCE two pipe support
v2: rebase by Marek
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=22f71dbf7976d1803940bc2a0429c3d302dae9fa
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Mar 12 16:24:57 2015 -0400
radeon/uvd: make 30M as minimum for MPEG4 dpb buffer size
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=baecc518c9adcd073e725268421a049dd610d22f
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Mar 12 16:13:44 2015 -0400
radeon/uvd: recalculate dbp buffer size
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c29f0d4722832a9d284aba899875955e60a41c03
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Mar 9 16:24:48 2015 -0400
radeon/video: add 4K support for decode/encode parameters
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=261ed775475db8d328a772fc4ff151d63969c84a
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Dec 15 12:51:50 2014 -0500
gallium/radeon: add h264 performance HW decoder support
v2: -make tonga use new h264 performance HW decoder;
-integrate it scaling buffer to msg_fb buffer
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67586c4b40881940535658c3c89b5b1a42f94027
Author: Christian König <christian.koenig at amd.com>
Date: Thu Apr 10 17:18:32 2014 +0200
gallium/radeon: use VM for VCE
v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek
Signed-off-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0248c13a8b1e10e2c8c8d614473c701239627a71
Author: Christian König <christian.koenig at amd.com>
Date: Wed Apr 9 19:41:06 2014 +0200
gallium/radeon: use VM for UVD
v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek
Signed-off-by: Christian König <christian.koenig at amd.com>
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=767ad50a10d01274b1d1a877add12b5552ba6984
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jul 29 15:40:46 2015 -0400
radeonsi: add support for FIJI (v4)
v2: incorporate comments from Marek
v3: add missing fiji case in winsys init
use tonga raster config (double check this)
v4: rebase on harvest patch
Reviewed-by: Marek Olšák <marek.olsak at amd.com> (v3)
Reviewed-by: Christian König <christian.koenig at amd.com> (v3)
Reviewed-by: David Zhang <david1.zhang at amd.com> (v3)
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=528a6ff5992e6710921d6e4157a8a51884bc277f
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Tue Jul 7 22:18:13 2015 -0400
winsys/amdgpu: add addrlib support for Fiji (v2)
v2: fix tonga chip check
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Reviewed-by: David Zhang <david1.zhang at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d69686f1d375c3a65a4398f69da843e833987b0e
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jul 8 22:19:55 2015 -0400
radeonsi: add harvest support for CI/VI parts (v3)
Properly calculate the PA_SC_RASTER_CONFIG[_1] settings
for harvest chips.
v2: - fix default raster config settings for CZ and KV
- Suggestions from Michel
v3: - handle multiple packers properly for CI+
- GRBM_GFX_INDEX is privileged on VI+
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com> (v2)
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=933d24b1768d769f1847a023ea3c70b6c9723e33
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 13:57:25 2015 +0200
gallium/radeon: enable the GPU load query for amdgpu
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0e24a7beae57f24501fa9d3b6b947fc20ca23bb
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jun 10 11:43:24 2015 -0400
radeonsi: properly handler raster_config setup on CZ
Need to take into account the number of RBs.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=649975e7162cc4ee0586ee76d24321cd7250581f
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Jun 10 11:39:30 2015 -0400
radeonsi: properly set the raster_config for KV
This enables the second RB on asics that support it which
should boost performance.
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
Cc: mesa-stable at lists.freedesktop.org
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf2c3422d7c12bdead944c3de8b37b809f4cbcbb
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 30 17:02:38 2015 +0200
radeonsi: add amdgpu support for querying the GPU reset state
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d1952e2a5abd273983374b420371d263388bb20
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:44:54 2015 +0200
radeonsi: add VI hardware support
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=943a4b5e963a3bbeb3a0a39d0123e359fdf3ec07
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jul 11 13:22:22 2015 +0200
radeonsi: add definitions for VI status registers
Useful for debugging hangs with the read-register interface.
I checked that this adds the same register fields as the kernel driver.
Acked-by: Michel Dänzer <michel.daenzer at amd.com>
Acked-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f49f6ed19ba4ee6a26c77786dcbc151c6615d48
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:12:24 2015 +0200
radeonsi: add VI register definitions
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ba70e0a7405005c079eb72f94999245c992aa91
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 20:35:27 2015 +0200
radeonsi: fix DRM version checks for amdgpu DRM 3.0.0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7fc664b91a5d886c2709d05a498f6a1dfbaf136
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 19:41:33 2015 +0200
winsys/amdgpu: add addrlib - texture addressing and alignment calculator
This is an internal project that Catalyst uses and now open source will do
too.
v2: squashed these commits in:
- winsys/amdgpu: fix warnings in addrlib
- winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eb067db0febcd71b4182153155e3e43f215624c
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Apr 16 22:43:23 2015 +0200
winsys/amdgpu: add a new winsys for the new kernel driver
v2: - lots of changes according to Emil Velikov's comments
- implemented radeon_winsys::read_registers
v3: - a lot of new work, many of them adapt to libdrm interface changes
Squashed patches:
winsys/amdgpu: implement radeon_winsys context support
winsys/amdgpu: add reference counting for contexts
winsys/amdgpu: add userptr support
winsys/amdgpu: allocate IBs like normal buffers
winsys/amdgpu: add IBs to the buffer list, adapt to interface changes
winsys/amdgpu: don't use KMS handles as reloc hash keys
winsys/amdgpu: sync buffer accesses to different rings
winsys/amdgpu: use dependencies instead of waiting for last fence v2
gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface (amdgpu part)
winsys/amdgpu: track fences per ring and be thread-safe
winsys/amdgpu: simplify waiting on a variable in amdgpu_fence_wait
gallium/radeon: allow the winsys to choose the IB size (amdgpu part)
winsys/amdgpu: switch to new amdgpu_cs_query_fence_status interface
winsys/amdgpu: handle fence and dependencies merge
winsys/amdgpu follow libdrm change to move user fence into UMD
winsys/amdgpu: use amdgpu_bo_va_op for va map/unmap v2
winsys/amdgpu: use the new tiling flags
winsys/amdgpu: switch to new GTT_USWC definition
winsys/amdgpu: expose amdgpu_cs_query_reset_state to drivers
winsys/amdgpu: fix valgrind warnings
winsys/amdgpu: don't use VRAM with APUs that don't have much of it
winsys/amdgpu: require LLVM 3.6.1 for VI because of bug fixes there
winsys/amdgpu: remove amdgpu_winsys::num_cpus
winsys/amdgpu: align BO size to page size
winsys/amdgpu: reduce BO cache timeout
winsys/amdgpu: remove useless flushing and waiting in amdgpu_bo_set_tiling
winsys/amdgpu: use amdgpu_device_handle as a unique device ID instead of fd
winsys/amdgpu: use safer access to amdgpu_fence_wait::signalled
winsys/amdgpu: allow maximum IB size of 4 MB
winsys/amdgpu: add ip_instance into amdgpu_fence
gallium/radeon: add RING_COMPUTE instead of RADEON_FLUSH_COMPUTE
winsys/amdgpu: set the ring type at CS initilization
winsys/amdgpu: query the GART page size from the kernel
winsys/amdgpu: correctly wait for shared buffers to become idle
winsys/amdgpu: set the amdgpu_cs_fence structure only once at fence creation
winsys/amdgpu: add a specific error message for cs_submit -> -ENOMEM
winsys/amdgpu: check num_active_ioctls before calling amdgpu_bo_wait_for_idle
winsys/amdgpu: clear user fence BO after allocating it
winsys/amdgpu: fix user fences
winsys/amdgpu: make amdgpu_winsys_create public
winsys/amdgpu: remove thread offloading
winsys/amdgpu: flatten the amdgpu_cs_context structure and simplify more
v4: require libdrm 2.4.63
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5609a6986f3eb3c452d66d373b6081df5c6fb34c
Author: Christian König <christian.koenig at amd.com>
Date: Wed Apr 29 15:35:02 2015 +0200
st/vdpau: add HEVC support v2
v2: fix return code
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5581f9f28aeaef63bc1495febb402435ddfde556
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 13:19:56 2015 -0400
st/omx/enc: stack frame tasks for the gathering
Put tasks to the FIFO queue for results
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0729c251bbff8375ab5d24b80cfc2f8becd6afff
Author: Leo Liu <leo.liu at amd.com>
Date: Fri May 29 14:50:44 2015 -0400
st/omx/enc: flush after eos handling v2
v2 (chk): reorder the flush
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=facba49d839b01da139261e587a05c744cc9a1fa
Author: Christian König <christian.koenig at amd.com>
Date: Tue Apr 28 15:31:37 2015 +0200
vl: add HEVC profiles and defines
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Leo Liu <leo.liu at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=716a67da12be0656a6dae2a448175946aaf57377
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 12:09:11 2015 -0400
vl: add cap for stacking frames
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=973988ab8dd4d04b925a5859d1da0801e858a6fe
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Aug 13 01:51:37 2015 +0200
swrast: fix EXT_depth_bounds_test
zMin and zMax can't use _DepthMaxF, because the test is done in Z32_UNORM.
Probably a useless patch given how popular swrast is nowadays, but it helped
create and validate the piglit test.
v2: add an explicit cast to GLuint
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97f58fb59a45f04c9d03709063a081f572509f51
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 02:23:21 2015 +0200
radeonsi: add support for EXT_depth_bounds_test
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36a6f848bb03828aa9c4dc28774acf09055f2831
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 02:18:43 2015 +0200
st/mesa: add EXT_depth_bounds_test
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b7800e75089d4dc8ed9b2a0ce994760c167b93a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 02:11:48 2015 +0200
gallium: add an interface for EXT_depth_bounds_test
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
Reviewed-by: Brian Paul <brianp at vmware.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ebb8efa08b4ea290b8a2bb9aa2e3784b8272d87
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 19:53:22 2015 +0200
st/mesa: small cleanup in st_extensions.c
Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=44dc1d307d7eacef0d6f1618ba0fb7f62e08f896
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Aug 10 19:37:01 2015 +0200
gallium: add support for GLES texture float extensions (v3)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=74329
v2: add a CAP for half floats
drivers should not expose the CAPs if they don't support the formats
v3: update relnotes
Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland at vmware.com>
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