Mesa (11.0): 23 new commits

Mon Aug 31 14:52:53 UTC 2015

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f8d44210c70f4b16651f1faf5fd72c47c64ab07
Author: Emil Velikov <emil.l.velikov at gmail.com>
Date:   Mon Aug 31 13:40:19 2015 +0100

    Update version to 11.0.0-rc2
    
    Signed-off-by: Emil Velikov <emil.l.velikov at gmail.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=579ca506aefabc018d2cdd1856de4ce0e95bdfcf
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Aug 23 12:57:09 2015 +0200

    gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packets
    
    Cc: mesa-stable at lists.freedesktop.org
    Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
    (cherry picked from commit 437cb1e3f482570447501526927df4d80c845bf5)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=94205d0aa229d0cbfb9a5f9ed0cbd1cb07ba9d33
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Mon Aug 24 23:31:00 2015 -0400

    freedreno/a3xx: add basic clip plane support
    
    The hardware is capable of dealing with GL1-style user clip planes.
    No clip vertex, no clip distances. Fixes a number of ucp tests, as well
    as neverball.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit 58e24b4761ec8c348bf6825c2355a6e047599306)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b40221850d41b622e66f7bbea0eed6594b85c4a
Author: Dave Airlie <airlied at redhat.com>
Date:   Fri Aug 28 10:46:10 2015 +1000

    r600: port si_conv_prim_to_gs_out from radeonsi
    
    This code was broken by the tess merge, and I totally missed it
    until now. I'm not sure this fixes anything but it stops the assert.
    
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Glenn Kennard <glenn.kennard at gmail.com>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit 6941883175612ae602a8745945153ba064f53a7a)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fe87a1b68c282846c119bdd930aa936c6504054
Author: Dave Airlie <airlied at redhat.com>
Date:   Fri Aug 28 09:57:04 2015 +1000

    gallium/util: fix debug_get_flags_option on 32-bit
    
    On 32-bit we need to use PRIu64 flags for printfs,
    otherwise this segfaults in R600_DEBUG=help otherwise.
    
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit 8d6d0cc17d945317f44328a7761801e6781dc3fc)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b83b452eea6db023f50611e090f05c5dcafdbc93
Author: Daniel Scharrer <daniel at constexpr.org>
Date:   Fri Aug 28 11:45:35 2015 +0200

    mesa: add missing queries for ARB_direct_state_access
    
    This adds index queries (glGet*i_v) for GL_TEXTURE_BINDING_* and
    GL_SAMPLER_BINDING, as well as textue queries
    (glGetTex{,ture}Parameter*) for GL_TEXTURE_TARGET.
    
    CC: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
    
    Reviewed-by: Fredrik Höglund <fredrik at kde.org>
    Signed-off-by: Fredrik Höglund <fredrik at kde.org>
    (cherry picked from commit 5aaaaebf22c920745d577c49e463d23b90ba5ea8)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=68bd2ddda026afd5e45324d51a5b6b74227c5408
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date:   Thu Aug 27 19:04:17 2015 +0200

    r600g/sb: Don't crash on empty if jump target
    
    Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
    Cc: <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit 608c7b4a63d5818f7ae0b3d48496b02cf8458d9b)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9db5c2ca2ea8f4172611337db1cc81f19aab443e
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date:   Thu Aug 27 19:04:16 2015 +0200

    r600g/sb: Don't read junk after EOP
    
    Shaders that contain instruction data after an instruction with EOP could end
    up parsing that as an instruction, leading to various crashes and asserts in
    SB as it gets very confused if it sees for instance a loop start instruction
    jumping off to some random point.
    
    Add a couple of asserts, and print EOP bit if set in old asm printer.
    
    Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
    Cc: <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit a830225adbb77073272961df409885cca6b861ee)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=08c41221d7102106d0b70a6399e2270919458077
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date:   Thu Aug 27 19:04:15 2015 +0200

    r600g/sb: Handle undef in read port tracker
    
    e8e443 missed adding check for undef values also in
    unreserve function, leading to an assert triggering.
    
    Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
    Cc: <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit 36f1999a87258603b6720d55e6020d5d24c215c9)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=896ef5cb95557fbf68c75600d2bcbb01f8933b98
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Thu Aug 27 15:28:24 2015 -0400

    mesa: only copy the requested teximage faces
    
    Cube maps are special in that they have separate teximages for each
    face. We handled that by copying the data to them separately, but in
    case zoffset != 0 or depth != 6 we would read off the end of the client
    array or modify the wrong images.
    
    zoffset/depth have already been verified by the time the code gets to
    this stage, so no need to double-check.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Reviewed-by: Brian Paul <brianp at vmware.com>
    Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit 2259b111003f2e8c55cae42677ec45345fb1b6e3)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=594388e5776312c1bdc9d5613369ed530bb7fbbc
Author: Jason Ekstrand <jason.ekstrand at intel.com>
Date:   Wed Aug 19 14:29:53 2015 -0700

    i965/fs: Split VGRFs after lowering pull constants
    
    The split_virtual_grfs code doesn't properly rewrite reladdr so we need to
    make sure that any uniform indirects are lowered away first.
    
    This fixes the glsl-fs-uniform-indexed-by-swizzled-vec4.shader_test in piglit
    
    Cc: "10.6" <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
    (cherry picked from commit fee0c5af11dd0995de96e7053377d425a66d03a0)
    
    Conflicts:
    	src/mesa/drivers/dri/i965/brw_fs.cpp

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=812f2855dd601e23a4f813f53547d446ca484df7
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Aug 24 00:22:37 2015 +0200

    mesa: create multisample fallback textures like normal textures
    
    This works if drivers upsample on upload (like all radeon ones do).
    The alternative is an unexpected GL error from anything calling
    _mesa_update_state and possibly other issues.
    
    Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit f432ae899fb81468778dbeb17ac7615da3ed5c0d)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d8ce45d9031e9949dfbab27ab4d608853b86d72
Author: Dave Airlie <airlied at redhat.com>
Date:   Mon Aug 24 09:52:12 2015 +1000

    mesa/texgetimage: fix missing stencil check
    
    GetTexImage can read to stencil8 but only from
    a stencil or depthstencil textures.
    
    This fixes a bunch of failures in CTS
    GL33-CTS.gtf32.GL3Tests.packed_pixels
    
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit c1452983b44cc8ee238b8c7e2cfca1105c707487)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=33b0f6e5e181c52c3eeb7ba4cb3bc0db13f10670
Author: Dave Airlie <airlied at redhat.com>
Date:   Wed Jul 29 18:09:44 2015 +1000

    mesa: enable texture stencil8 for multisample
    
    This fixes GL45-CTS.gtf44.GL31Tests.texture_stencil8.texture_stencil8_gl44
    from the ogl conform suite.
    
    Reviewed-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Cc: 10.6 11.0 <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit 529acab22a3e21e0ed0c5243675aec6c0ee27e8f)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6659fba2c0ea9a5c358e3ef3770585381e619d39
Author: Chris Wilson <chris at chris-wilson.co.uk>
Date:   Sun Aug 23 09:24:57 2015 +0100

    i965: Always re-emit the pipeline select during invariant state emission
    
    On the older platforms where we don't have logical contexts preserving
    state across batches, we emit the invariant state setup on every batch
    using the brw_invariant_state atom. This includes the pipeline selection
    which is cached with the introduction of
    
    commit 0e0e23ef537c9add672ff322f34e129a07edc55e
    Author: Jordan Justen <jordan.l.justen at intel.com>
    Date:   Wed Apr 22 11:43:50 2015 -0700
    
        i965/state: Emit pipeline select when changing pipelines
    
    However, we do not reset the cache between batches on context-less
    platforms resulting in us not setting the pipeline selection and can
    cause GPU hangs if a media pipelined was loaded in the meantime (e.g.
    mixing mplayer/gstreamer using libva and gnome-shell). A simple solution
    is to just forcibly re-emit the pipeline select along with the invariant
    state and reset the cache at that point.
    
    Reported-and-tested-by: Tomasz C. <tomaszc at o2.pl>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254
    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
    Cc: Jordan Justen <jordan.l.justen at intel.com>
    Cc: Kenneth Graunke <kenneth at whitecape.org>
    Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
    Cc: "10.6 11.0" <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit 4e5752e2b78243a71766538f62ca0a80488047a7)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=adae777f24fd84d3a0c074c5f2c01a31d9f63cce
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Aug 23 18:57:44 2015 +0200

    Revert "radeon/winsys: increase the IB size for VM"
    
    This reverts commit 567394112d904096abff1d994ab952f475dfb444.
    
    It regressed performance. It looks like smaller IBs are better, because
    the GPU goes idle quicker and there is less waiting for buffers and fences.
    
    Cc: 11.0 <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit a83c36b5c0c64c717ced76db89bab900006648aa)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b690e39dc3f84dbce97d507fd7955ecdecbe5c2
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sun Aug 23 03:11:09 2015 -0400

    nv50: fix 2d engine blits for 64- and 128-bit formats
    
    This fixes bin/ext_framebuffer_multisample-formats all_samples
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit e18c29b03105567cf20bc235ce23cf08986cc537)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=67fc4b417a7e73feb840b6666b343f4d32d23f22
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sun Aug 23 02:56:45 2015 -0400

    nv50: account for the int RT0 rule for alpha-to-one/cov
    
    Same as commit 1af0641db but for nvc0. If an integer texture is
    bound to RT0, don't do alpha-to-one or alpha-to-coverage.
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit a6ad49cbbd599aec054d0a3163fff5ad724f2b18)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a8d2048bc830c77be7baf5eb71aaef645cb1bf6
Author: Dave Airlie <airlied at redhat.com>
Date:   Mon Jul 27 13:13:49 2015 +1000

    mesa/arb_gpu_shader_fp64: add support for glGetUniformdv
    
    This was missed when I did fp64, I've sent a piglit test to cover
    the case as well.
    
    Reviewed-by: Timothy Arceri <t_arceri at yahoo.com.au>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at redhat.com>
    (cherry picked from commit 45971fd0df1cbfc400f89f2e8df206625b40d65f)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf84c85130d7b9160f62ce8b54e33d5228531217
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date:   Sat Aug 22 23:59:50 2015 -0400

    nv50,nvc0: disable depth bounds test on blit
    
    Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    (cherry picked from commit abbf05cfc2bea0787bcf710ef984d73ee8ba8f9e)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aab6075613ec078257cc7008e40319f844d2ba9c
Author: Neil Roberts <neil at linux.intel.com>
Date:   Wed Aug 19 18:55:44 2015 -0700

    i965/bdw: Fix 3DSTATE_VF_INSTANCING when the edge flag is used
    
    When the edge flag element is enabled then the elements are slightly
    reordered so that the edge flag is always the last one. This was
    confusing the code to upload the 3DSTATE_VF_INSTANCING state because
    that is uploaded with a separate loop which has an instruction for
    each element. The indices used in these instructions weren't taking
    into account the reordering so the state would be incorrect.
    
    v2: Use nr_elements instead of brw->vb.nr_enabled so that it will cope
        when gl_VertexID is used.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91292
    Cc: <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
    Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
    Tested-by: Mark Janes <mark.a.janes at intel.com>
    (cherry picked from commit 3a1ab2348050fd32f41553b9febfd9972b5761aa)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ef343432828f563d793908af6e1b0401d6cba5a
Author: Neil Roberts <neil at linux.intel.com>
Date:   Mon Jul 13 18:01:14 2015 +0100

    i965: Swap the order of the vertex ID and edge flag attributes
    
    The edge flag data on Gen6+ is passed through the fixed function hardware as
    an extra attribute. According to the PRM it must be the last valid
    VERTEX_ELEMENT structure. However if the vertex ID is also used then another
    extra element is added to source the VID. This made it so the vertex ID is in
    the wrong register in the vertex shader and the edge attribute is no longer in
    the last element.
    
    v2: Also implement for BDW+
    
    v3 [by Ben]: Remove 10.5 tag. Too late.
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84677
    Cc: <mesa-stable at lists.freedesktop.org>
    Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
    Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
    Tested-by: Ben Widawsky <ben at bwidawsk.net>
    Tested-by: Mark Janes <mark.a.janes at intel.com>
    (cherry picked from commit fb02b4ec482762ccf2a9fedf24fe6f50787932a9)

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d58fea2e39e406ae0a4183317170451813f7794
Author: Glenn Kennard <glenn.kennard at gmail.com>
Date:   Sun Aug 23 01:01:31 2015 +0200

    r600g: Fix assert in tgsi_cmp
    
    Fixes https://bugs.freedesktop.org/show_bug.cgi?id=91726
    
    Signed-off-by: Glenn Kennard <glenn.kennard at gmail.com>
    Cc: "11.0" <mesa-stable at lists.freedesktop.org>
    Signed-off-by: Dave Airlie <airlied at gmail.com>
    (cherry picked from commit 50932268aad0cc21511f370793e77c76e038bd06)