Mesa (master): 28 new commits
Francisco Jerez
currojerez at kemper.freedesktop.org
Tue Feb 10 17:13:48 UTC 2015
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b224290fbf8f4f4ccf933a6281276931ccec9b8
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 22 18:35:46 2013 -0800
i965/gen7-8: Implement glMemoryBarrier().
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=46b03d5400794736e04eee5d373673309ba286ad
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 10 15:53:14 2015 +0200
i965: Generalize the update_null_renderbuffer_surface vtbl hook to non-renderbuffers.
Null surfaces are going to be useful to have something to point
unbound image units to, as the ARB_shader_image_load_store extension
requires us to behave deterministically in cases where some shader
tries to access an unbound image unit: Invalid stores and atomics are
supposed to be discarded and invalid loads are supposed to return
zero, which is precisely what the null surface does.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=342b7ce7d4383db3f956e207f189376a94b359fe
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 22 16:08:12 2013 -0800
i965: Allocate binding table space for shader images.
v2: Bump the number of supported image uniforms to 32 (Ken).
Reviewed-by: Paul Berry <stereotype441 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36a17f0f991323410778392bc2d00f9d911d501b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Nov 14 20:30:46 2014 +0200
i965: Don't tile 1D miptrees.
It doesn't really improve locality of texture fetches, quite the
opposite it's a waste of memory bandwidth and space due to tile
alignment.
v2: Check mt->logical_height0 instead of mt->target (Ken). Add short
comment explaining why they shouldn't be tiled.
Reviewed-by: Neil Roberts <neil at linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b40bcd24e0c86fb02c226261c1fe46fb362be217
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Feb 4 18:37:46 2015 +0200
i965/vec4: Don't set any dependency control bits for F32TO16 on Gen8.
It's expanded to several instructions.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aef83957e1e13ecb96df436d53373ecc4cedeb08
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 14:38:20 2015 +0200
i965: Handle negated unsigned immediate values in constant propagation.
Negation of UD/UW sources behaves the same as for D/W sources, taking
the two's complement of the source, except for bitwise logical
operations on Gen8 and up which take the one's complement. Fixes
crash in a GLSL shader with subtraction of two unsigned values.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=64fde7b31c419685aa8ef6060828e21b9a11ef51
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 22:50:06 2015 +0200
i965/vec4: Take into account non-zero reg_offset during register allocation.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=78e9043475d4bed8b50f7e413963c960fa0935bb
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 20:34:39 2015 +0200
i965/vec4: Add register classes up to MAX_VGRF_SIZE.
In preparation for some send from GRF instructions that will require
larger payloads.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=530445330b403d835a4027b41388b5eea8c2e1ab
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 22:52:37 2015 +0200
i965/vec4: Init mlen for several send from GRF instructions.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f878d1b470e5307ec18ca409e73b1a81e8361fa
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 22:42:23 2015 +0200
i965/vec4: Don't infer MRF dependencies for send from GRF instructions.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de666fc102b805707c7033b203c5b76ccbbcef8d
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 5 22:39:33 2015 +0200
i965/vec4: Fix the scheduler to take into account reads and writes of multiple registers.
v2: Avoid nested ternary operators in vec4_instruction::regs_read(). (Matt)
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ad486077e122c19b603750e19dd678bb7793d5b
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 5 22:58:03 2015 +0200
i965/vec4: Make vec4_visitor::implied_mrf_writes() return zero for sends from GRF.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16b911257440afbd77a6eb762e28df62e3c19bc7
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 22:53:17 2015 +0200
i965/vec4: Pass dst register to the vec4_instruction constructor.
So regs_written gets initialized with a sensible value.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c902a8f7875a547cea179e5324f5d2fd3990bcf
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 15:31:46 2015 +0200
i965/vec4: Initialize vec4_instruction::predicate and ::predicate_inverse.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=388b136e677e30249e062145b488c2d938c1ef17
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Feb 5 22:40:07 2015 +0200
i965/vec4: Implement equals() method for dst_reg too.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3df2cb2f863836ec909f5259693c1eeef675a594
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 21:57:38 2015 +0200
i965/fs: Fix fs_inst::regs_written calculation for instructions with scalar dst.
Scalar registers are required to have zero stride, fix the
regs_written calculation not to assume that the instruction writes
zero registers in that case.
v2: Rename CEILING() to DIV_ROUND_UP(). (Matt, Ken)
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2668f9f214201503419342b980d3afa8b796926
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 01:14:51 2015 +0200
i965/fs: Fix stack allocation of fs_inst and stop stealing src array provided on construction.
Using 'ralloc*(this, ...)' is wrong if the object has automatic
storage or was allocated through any other means. Use normal dynamic
memory instead.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c472793a2a55bb529bf4297f04ff785ce52cfc6e
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 3 15:52:37 2015 +0200
i965/fs: Remove duplicate include of brw_shader.h
The second one was inside an extern "C" block, luckily it was being
discarded by the preprocessor.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfe957c02b753dbb5b372e768a5677f577daf9ef
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 01:28:12 2015 +0200
i965: Move up fs_inst::flag_subreg to backend_instruction.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=639696aa05df0b7f4bfb9e2e255863cd72effba3
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 01:27:40 2015 +0200
i965: Move up fs_inst::regs_written to backend_instruction.
It will also be useful in the VEC4 back-end.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ed52e8bc418b7a378c31664343684e4401e0868
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 01:25:50 2015 +0200
i965/vec4: Remove dependency of vec4_instruction on the visitor class.
The only reason why you need a vec4_visitor to construct a
vec4_instruction is to initialize vec4_instruction::ir and
::annotation. Instead set them from vec4_visitor::emit() just like
fs_visitor does.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3ee6c7d1991a90d22fae992c1cb94123e51ae54
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 01:24:17 2015 +0200
i965/fs: Remove dependency of fs_inst on the visitor class.
The fs_visitor argument of fs_inst::regs_read() wasn't used at all.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfbb0e84e11e06af3d751701f157a21915976ca1
Author: Francisco Jerez <currojerez at riseup.net>
Date: Fri Feb 6 01:11:18 2015 +0200
i965: Move IR object definitions to separate header files.
One should be able to manipulate i965 IR without pulling the whole
FS/VEC4 visitor classes -- Optimization passes and other
transformations would ideally be visitor-agnostic. Among other issues
this avoids a circular dependency between the header file where such
visitor-agnostic code will be defined and the main FS/VEC4 header
where both IR (layer below) and visitor (layer above) happen to be
defined.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=447879eb88b8df41ad32cf4406cc636b112b72d9
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 10 15:51:34 2015 +0200
i965: Factor out virtual GRF allocation to a separate object.
Right now virtual GRF book-keeping and allocation is performed in each
visitor class separately (among other hundred different things),
leading to duplicated logic in each visitor and preventing layering as
it forces any code that manipulates i965 IR and needs to allocate
virtual registers to depend on the specific visitor that happens to be
used to translate from GLSL IR.
v2: Use realloc()/free() to allocate VGRF book-keeping arrays (Connor).
Reviewed-by: Matt Turner <mattst88 at gmail.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6146e6f14d5e2f9080ce033814fb1d14a175e70
Author: Francisco Jerez <currojerez at riseup.net>
Date: Thu Dec 4 10:40:56 2014 +0200
glsl: Forbid calling the constructor of any opaque type.
The spec doesn't define any opaque type constructors.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4111dfa0a54238510a0c6374d6eb421c296d64f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Wed Nov 19 18:22:07 2014 +0200
glsl: Return correct number of coordinate components for cubemap array images.
Cubemap array images are unlike cubemap array samplers in that they don't need
an additional coordinate to index individual cubemaps in the array, instead
they behave like a 2D array of 6n layers, with n the number of cubemaps in the
array. Take this exception into account.
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcc2fd53df2d57a335856ebd7e01878d7a0d4de2
Author: Francisco Jerez <currojerez at riseup.net>
Date: Mon Feb 9 18:31:03 2015 +0200
mesa: Bump MAX_IMAGE_UNIFORMS to 32.
So the i965 driver can expose 32 image uniforms per shader stage.
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=818585b9f9ccd55b992e35f4d74120f0e879559f
Author: Francisco Jerez <currojerez at riseup.net>
Date: Tue Feb 10 15:37:47 2015 +0200
mesa: Rename the CEILING() macro to DIV_ROUND_UP().
Some people have complained that code using the CEILING() macro is
difficult to understand because it's not immediately obvious what it
is supposed to do until you go and look up its definition. Use a more
descriptive name that matches the similar utility macro in the Linux
kernel.
Reviewed-by: Matt Turner <mattst88 at gmail.com>
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