Mesa (master): radeonsi: initialize TC_L2_dirty to false after buffer allocation

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 218b15715ec6a9e987ae78d904683801e5ccdf4b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=218b15715ec6a9e987ae78d904683801e5ccdf4b

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Tue Feb 10 14:16:56 2015 +0100

radeonsi: initialize TC_L2_dirty to false after buffer allocation

I forgot to do this, though "true" should have no effect on correctness.

Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>

---

 src/gallium/drivers/radeon/r600_buffer_common.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index b7306d7..ebe8067 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -185,6 +185,7 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
 	pb_reference(&old_buf, NULL);
 
 	util_range_set_empty(&res->valid_buffer_range);
+	res->TC_L2_dirty = false;
 
 	if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
 		fprintf(stderr, "VM start=0x%"PRIX64"  end=0x%"PRIX64" | Buffer %u bytes\n",