Mesa (master): i965: Make scheduler cycle estimates use the proper stage name.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: eeacbc1a02ba2d8b9049d1108abcbd2b3dfe2712
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eeacbc1a02ba2d8b9049d1108abcbd2b3dfe2712

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Wed Feb 18 17:45:51 2015 -0800

i965: Make scheduler cycle estimates use the proper stage name.

Previously, the vec4 backend labeled shaders as "vec4" - now it uses the
specific names "VS" and "GS".

The FS backend now correctly prints "VS" for vertex shaders (rather than
"fs").  It also prints "FS" instead of "fs" for fragment shaders;
preserving that behavior didn't seem essential.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Kristian Høgsberg <krh at bitplanet.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp |   11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 24075bd..56f69ea 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -1517,9 +1517,9 @@ fs_visitor::schedule_instructions(instruction_scheduler_mode mode)
    fs_instruction_scheduler sched(this, grf_count, mode);
    sched.run(cfg);
 
-   if (unlikely(INTEL_DEBUG & DEBUG_WM) && mode == SCHEDULE_POST) {
-      fprintf(stderr, "fs%d estimated execution time: %d cycles\n",
-             dispatch_width, sched.time);
+   if (unlikely(debug_enabled) && mode == SCHEDULE_POST) {
+      fprintf(stderr, "%s%d estimated execution time: %d cycles\n",
+              stage_abbrev, dispatch_width, sched.time);
    }
 
    invalidate_live_intervals();
@@ -1531,8 +1531,9 @@ vec4_visitor::opt_schedule_instructions()
    vec4_instruction_scheduler sched(this, prog_data->total_grf);
    sched.run(cfg);
 
-   if (unlikely(debug_flag)) {
-      fprintf(stderr, "vec4 estimated execution time: %d cycles\n", sched.time);
+   if (unlikely(debug_enabled)) {
+      fprintf(stderr, "%s estimated execution time: %d cycles\n",
+              stage_abbrev, sched.time);
    }
 
    invalidate_live_intervals();