Mesa (master): i965: Don't force x-tiling for 16-bpp formats on Gen>7
Neil Roberts
nroberts at kemper.freedesktop.org
Wed Feb 25 13:23:43 UTC 2015
Module: Mesa
Branch: master
Commit: 67e3302497e90a4602921b4ac4621e97df60f850
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=67e3302497e90a4602921b4ac4621e97df60f850
Author: Neil Roberts <neil at linux.intel.com>
Date: Thu Feb 19 16:09:41 2015 +0000
i965: Don't force x-tiling for 16-bpp formats on Gen>7
Sandybridge doesn't support y-tiling for surface formats with 16 or
more bpp. There was previously an override to explicitly allow this
for Gen7. However, this restriction is also removed in Gen8+ so we
should use y-tiling there too.
This is important to do for Skylake which doesn't support x-tiling for
3D surfaces.
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 0e3888f..e085841 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -515,10 +515,10 @@ intel_miptree_choose_tiling(struct brw_context *brw,
/* From the Sandybridge PRM, Volume 1, Part 2, page 32:
* "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX
* or Linear."
- * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
- * all the way back to 965, but is explicitly permitted on Gen7.
+ * 128 bits per pixel translates to 16 bytes per pixel. This is necessary
+ * all the way back to 965, but is permitted on Gen7+.
*/
- if (brw->gen != 7 && mt->cpp >= 16)
+ if (brw->gen < 7 && mt->cpp >= 16)
return I915_TILING_X;
/* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most
More information about the mesa-commit
mailing list