Mesa (master): i965: Add QWORD sizes to type_sz macro

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 9394f5838364e3265b8f7ee87f3265848317e955
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9394f5838364e3265b8f7ee87f3265848317e955

Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Mon Dec 22 19:29:13 2014 -0800

i965: Add QWORD sizes to type_sz macro

GEN8 added the QWORD as a valid type for certain operations on the EU.
In order to calculate the number of registers used one must have the type
size as part of the equation. Quoting the formula in the code:

   regs_written = (dst.width * dst.stride * type_sz(dst.type) + 31) / 32;

Adding this separately for bisection since there is no simple way to add
an assert in the type_sz function.

NOTE: As a side note, I was confused for a while because it's impossible
to calculate the region, ie. registers needed, without vstride.  However,
at this point these are all part of the IR, and so no vstride must exist.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_reg.h |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_reg.h b/src/mesa/drivers/dri/i965/brw_reg.h
index a04149c..76d3248 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++ b/src/mesa/drivers/dri/i965/brw_reg.h
@@ -171,6 +171,9 @@ static inline int
 type_sz(unsigned type)
 {
    switch(type) {
+   case BRW_REGISTER_TYPE_UQ:
+   case BRW_REGISTER_TYPE_Q:
+      return 8;
    case BRW_REGISTER_TYPE_UD:
    case BRW_REGISTER_TYPE_D:
    case BRW_REGISTER_TYPE_F: