Mesa (amdgpu): 33 new commits
Marek Olšák
mareko at kemper.freedesktop.org
Mon Jul 13 21:27:22 UTC 2015
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a9ab75914500b4d06b5133932521ce5edbf415c
Author: Christian König <christian.koenig at amd.com>
Date: Thu Jul 9 12:23:51 2015 +0200
winsys/amdgpu: handle fence and dependencies merge
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Jammy Zhou <Jammy.Zhou at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fa9bd4c6097ab5051c878b89be437dc4824f388
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jul 9 02:39:10 2015 +0200
winsys/radeon: fix build breakage since 248f552
I'm using CC="ccache gcc" and autoconf thinks that's not gcc, so it doesn't
add -Werror=implicit-function-declaration and I didn't get any error.
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8156fca044f1c31051ed533049bd00fa838262f
Author: Jammy Zhou <Jammy.Zhou at amd.com>
Date: Thu Jul 9 13:54:57 2015 +0800
winsys/amdgpu: switch to new amdgpu_cs_query_fence_status interface
Signed-off-by: Jammy Zhou <Jammy.Zhou at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5fccd1463ab7579410cffb701024b9d1757e3d0
Author: Marek Olšák <marek.olsak at amd.com>
Date: Tue Jun 30 11:34:16 2015 +0200
winsys/amdgpu: query the GART page size from the kernel
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d18cb66165f092624e9e1c39493ad0c75f8de5cc
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 15:19:36 2015 +0200
winsys/amdgpu: set the ring type at CS initilization
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=25bdc836adef29dea2e77fb877ff042d8f47327a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 15:14:11 2015 +0200
gallium/radeon: add RING_COMPUTE instead of RADEON_FLUSH_COMPUTE
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=207641614596792c8f67cd7660d7c189f2884673
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 15:06:25 2015 +0200
winsys/amdgpu: add ip_instance into amdgpu_fence
It's currently always 0.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf7de8c5745a05185070ec8abd36b2449d26d99b
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 14:49:34 2015 +0200
radeonsi: don't count the exact needed CS space if the CS is large enough
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2918f5b2358c5c090aed57c9f89162981ef96ae9
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 14:27:58 2015 +0200
winsys/amdgpu: allow maximum IB size of 4 MB
The IB space is sub-allocated on demand, so small IBs will only use
the space they need.
This is the limit for the CP. What about other IPs?
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f836fa3686aecad13b02e907fcb8b88947121606
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 14:19:41 2015 +0200
gallium/radeon: allow the winsys to choose the IB size
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ec475f649d7c55e4043feda71b15873e0ba5060
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 02:28:33 2015 +0200
winsys/amdgpu: use safer access to amdgpu_fence_wait::signalled
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=90a0fd6660ba0af02756a3d39d85031cdd407f9a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 02:26:01 2015 +0200
winsys/amdgpu: simplify waiting on a variable in amdgpu_fence_wait
The time waited doesn't have to be subtracted with the absolute timeout.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc61661de3fa705e0214d5adf4310b57e9066fa2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jun 25 22:58:22 2015 +0200
winsys/amdgpu: track fences per ring and be thread-safe
This is required for multi-ring support.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=248f5520c3cdbca7e42c8e5772d8b1c0815aa4b3
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jun 25 21:11:13 2015 +0200
gallium/radeon: unify buffer_wait and buffer_is_busy in the winsys interface
The timeout parameter covers both cases.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef897fbf343ffe47fbf8302fa32a927380965ed2
Author: Marek Olšák <marek.olsak at amd.com>
Date: Mon Jun 29 12:21:25 2015 +0200
winsys/amdgpu: use amdgpu_device_handle as a unique device ID instead of fd
We can use the unique-device-structure-per-fd mechanism from libdrm_amdgpu
for winsys creation by simply using amdgpu_device_handle as the device ID.
In other words, for each unique amdgpu_device_handle, assign a unique
winsys instance to it.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97cf648db4e3c3df8399b9d098cc6c317e07c73f
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jun 25 20:22:10 2015 +0200
winsys/amdgpu: remove useless flushing and waiting in amdgpu_bo_set_tiling
This was copied from radeon and it was required when the CS checker was
overwriting tiling flags in register packets. Pretty old code.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb39b8b28ad6e9877ec61be91574c60c5e216800
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 15:29:48 2015 +0200
winsys/amdgpu: reduce BO cache timeout
Backported from winsys/radeon commit 29aaab2b5f55cc6d9a84f5 made by
Grigori Goronzy <greg at chown.ath.cx>. From the commit:
1000 ms is an extreme value for typical interactive loads. A large
cache has some disadvantages. Search for reusable BOs can take a long
time and memory might get exhausted.
Let's be rather conservative and use half of the old value,
500ms. This is beneficial to some loads on my test system and there
are no regressions.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cf1316b7b95192c6ec2bc5ecf73807aece59022
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 15:28:29 2015 +0200
winsys/amdgpu: align BO size to page size
Backported from winsys/radeon commit 29aaab2b5f55cc6d9a84f5 made by
Grigori Goronzy <greg at chown.ath.cx>. From the commit:
This is the basic granularity for BO allocations. The alignment also
helps with BO reuse by the cached bufmgr.
This results in a huge 45% speedup in Metro 2033 Redux on my test
system. The game relies on buffer orphaning with very small buffers
(hundreds of bytes in size) and that did not work efficiently
before. This change may also affect other applications and games.
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=334ce55c5e9f72f7edd77d8b42f304e6841c488a
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 24 20:36:51 2015 +0200
winsys/amdgpu: remove amdgpu_winsys::num_cpus
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a760b9055bed0e4e588e774239968b8596cfadc1
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 14:03:46 2015 +0200
radeonsi: don't flush an empty IB if the only thing we need is a fence
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e52e427269a8853aaae1f15b81cd0ee062f256d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 13:57:25 2015 +0200
gallium/radeon: enable the GPU load query for amdgpu
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36ea76c1f0b98b685ad1305128ef954bbcd07e7d
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sat Jun 27 00:05:26 2015 +0200
gallium/os: add conversion and wait functions for absolute timeouts
Absolute timeouts are used with the amdgpu kernel driver.
It also makes waiting for several variables and fences at the same time
easier (the timeout doesn't have to be recalculated after every wait call).
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b06bccdb18595021a41b69e4f88fcf6b9163ae36
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu Jun 25 20:39:34 2015 +0200
gallium/os: add os_wait_until_zero (v2)
This will be used by radeon and amdgpu winsyses.
Copied from the amdgpu winsys.
v2: use volatile and p_atomic_read
Reviewed-by: Brian Paul <brianp at vmware.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33d9068e3b88b689b9c2fa3821a37aefc2a8346d
Author: Tom Stellard <thomas.stellard at amd.com>
Date: Thu Jun 11 15:42:25 2015 +0000
radeon/llvm: Handle LLVM backend rename from R600 to AMDGPU
Signed-off-by: Anatoli Antonovitch <anatoli.antonovitch at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
(cherry picked from commit 4d35eef326e49cc8da50879d30a1c5088d4775e1)
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=622ac9e68b2d60adc6992a17c2e62f3f4536310d
Author: Christian König <christian.koenig at amd.com>
Date: Wed Jun 24 14:20:33 2015 +0200
winsys/amdgpu: use dependencies instead of waiting for last fence v2
v2: move dependencies into amdgpu_cs_context
Signed-off-by: Christian König <christian.koenig at amd.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=30ee341e789840ab9dacac52c5e7bc3904b9d575
Author: Marek Olšák <marek.olsak at amd.com>
Date: Wed Jun 24 11:58:50 2015 +0200
radeonsi: fix a hang with DrawTransformFeedback on 4 SE chips
Cc: 10.6 10.5 <mesa-stable at lists.freedesktop.org>
Acked-by: Christian König <christain.koenig at amd.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=52654b3b6ca3dbeb4b1238fb9c7bcb33aab9717a
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 10:14:14 2015 -0400
radeon/vce: implement VCE dual instance support
VCE dual instances are encoding in parallel, it needs two frames for
encoding with their own parameters in one IB. Master instance will check
the task info to find another frame, assign it to the slave instance
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d71eee2c808987f59d7b32546817dcaa42582beb
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 13:19:56 2015 -0400
st/omx/enc: stack frame tasks for the gathering
Put tasks to the FIFO queue for results
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11b5ef3f480384f8277ddfd0b09d5195191bf44c
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 12:12:12 2015 -0400
radeon/video: config encode stacked frame number based on HW
since VCE 3.0 with dual instances, we need stack frames for them.
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6eb93c9721eae3e6e75324f7e4aa500e53394f22
Author: Leo Liu <leo.liu at amd.com>
Date: Thu Jun 25 12:09:11 2015 -0400
vl: add cap for stacking frames
Signed-off-by: Leo Liu <leo.liu at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5108a94bb56f65d75b0369241b1657d2d797133c
Author: Christian König <christian.koenig at amd.com>
Date: Mon Jun 15 20:19:48 2015 +0200
radeon/vce: make reloc offset signed
We need a negative offset for FW 50.
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3a45629bdd320b41d9c7542a942d3aa6e041842
Author: Leo Liu <leo.liu at amd.com>
Date: Mon Jun 1 13:48:24 2015 -0400
radeon/vce: add config task and put task info into encoder v2
The config task has own task ID, extract the configuration functions
into config task.
v2 (chk): calculate offset automatically
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e993eb4fd08546c400bcb39122ff6fe32fd82ad
Author: Leo Liu <leo.liu at amd.com>
Date: Fri May 29 14:50:44 2015 -0400
st/omx/enc: flush after eos handling v2
v2 (chk): reorder the flush
Signed-off-by: Leo Liu <leo.liu at amd.com>
Signed-off-by: Christian König <christian.koenig at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
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