Mesa (master): nvc0/ir: add hazard for 2nd dim of vfetch/ load indirect argument
Ilia Mirkin
imirkin at kemper.freedesktop.org
Thu Jul 23 07:44:26 UTC 2015
Module: Mesa
Branch: master
Commit: 77672cdb64e9c19e974fe5985050709fc317498e
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=77672cdb64e9c19e974fe5985050709fc317498e
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Thu Jul 23 02:27:04 2015 -0400
nvc0/ir: add hazard for 2nd dim of vfetch/load indirect argument
Apparently a multi-word load can potentially overwrite the indirect
sources, so make sure that RA picks different registers for those.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
index 898653c..78bc97f 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp
@@ -2066,6 +2066,8 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
condenseDefs(i);
if (i->src(0).isIndirect(0) && typeSizeof(i->dType) >= 8)
addHazard(i, i->src(0).getIndirect(0));
+ if (i->src(0).isIndirect(1) && typeSizeof(i->dType) >= 8)
+ addHazard(i, i->src(0).getIndirect(1));
} else
if (i->op == OP_UNION ||
i->op == OP_MERGE ||
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