Mesa (master): ilo: add generic ilo_render_pipe_control()
Chia-I Wu
olv at kemper.freedesktop.org
Fri Mar 6 19:29:21 UTC 2015
Module: Mesa
Branch: master
Commit: 8b2eecfbf8def8ef343529f7b0378dc1b8a36ff9
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b2eecfbf8def8ef343529f7b0378dc1b8a36ff9
Author: Chia-I Wu <olvaffe at gmail.com>
Date: Sat Mar 7 01:16:47 2015 +0800
ilo: add generic ilo_render_pipe_control()
It replaces gen[6-8]_pipe_control() and a direct gen6_PIPE_CONTROL() call in
ilo_render_emit_flush().
---
src/gallium/drivers/ilo/ilo_render.c | 5 +---
src/gallium/drivers/ilo/ilo_render_gen.h | 33 +++++++++++++++++++++
src/gallium/drivers/ilo/ilo_render_gen6.c | 34 +++++----------------
src/gallium/drivers/ilo/ilo_render_gen7.c | 46 ++++++-----------------------
src/gallium/drivers/ilo/ilo_render_gen8.c | 39 ++++--------------------
5 files changed, 56 insertions(+), 101 deletions(-)
diff --git a/src/gallium/drivers/ilo/ilo_render.c b/src/gallium/drivers/ilo/ilo_render.c
index a6614f1..af18e89 100644
--- a/src/gallium/drivers/ilo/ilo_render.c
+++ b/src/gallium/drivers/ilo/ilo_render.c
@@ -253,10 +253,7 @@ ilo_render_emit_flush(struct ilo_render *render)
if (ilo_dev_gen(render->dev) == ILO_GEN(6))
gen6_wa_pre_pipe_control(render, dw1);
- gen6_PIPE_CONTROL(render->builder, dw1, NULL, 0, 0);
-
- render->state.current_pipe_control_dw1 |= dw1;
- render->state.deferred_pipe_control_dw1 &= ~dw1;
+ ilo_render_pipe_control(render, dw1);
assert(ilo_builder_batch_used(render->builder) <= batch_used +
ilo_render_get_flush_len(render));
diff --git a/src/gallium/drivers/ilo/ilo_render_gen.h b/src/gallium/drivers/ilo/ilo_render_gen.h
index 583265f..9657798 100644
--- a/src/gallium/drivers/ilo/ilo_render_gen.h
+++ b/src/gallium/drivers/ilo/ilo_render_gen.h
@@ -30,6 +30,7 @@
#include "ilo_common.h"
#include "ilo_builder.h"
+#include "ilo_builder_render.h"
#include "ilo_state.h"
#include "ilo_render.h"
@@ -341,6 +342,38 @@ ilo_render_emit_launch_grid_surface_states(struct ilo_render *render,
const struct ilo_state_vector *vec,
struct ilo_render_launch_grid_session *session);
+/**
+ * A convenient wrapper for gen6_PIPE_CONTROL(). This should be enough for
+ * our needs everywhere except for queries.
+ */
+static inline void
+ilo_render_pipe_control(struct ilo_render *r, uint32_t dw1)
+{
+ const uint32_t write_mask = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK);
+ struct intel_bo *bo = (write_mask) ? r->workaround_bo : NULL;
+
+ ILO_DEV_ASSERT(r->dev, 6, 8);
+
+ if (write_mask)
+ assert(write_mask == GEN6_PIPE_CONTROL_WRITE_IMM);
+
+ if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
+ /* CS stall cannot be set alone */
+ const uint32_t mask = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
+ GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
+ GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
+ GEN6_PIPE_CONTROL_DEPTH_STALL |
+ GEN6_PIPE_CONTROL_WRITE__MASK;
+ if (!(dw1 & mask))
+ dw1 |= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
+ }
+
+ gen6_PIPE_CONTROL(r->builder, dw1, bo, 0, 0);
+
+ r->state.current_pipe_control_dw1 |= dw1;
+ r->state.deferred_pipe_control_dw1 &= ~dw1;
+}
+
void
gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1);
diff --git a/src/gallium/drivers/ilo/ilo_render_gen6.c b/src/gallium/drivers/ilo/ilo_render_gen6.c
index 7232882..898b98a 100644
--- a/src/gallium/drivers/ilo/ilo_render_gen6.c
+++ b/src/gallium/drivers/ilo/ilo_render_gen6.c
@@ -38,24 +38,6 @@
#include "ilo_state.h"
#include "ilo_render_gen.h"
-/**
- * A wrapper for gen6_PIPE_CONTROL().
- */
-static void
-gen6_pipe_control(struct ilo_render *r, uint32_t dw1)
-{
- struct intel_bo *bo = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) ?
- r->workaround_bo : NULL;
-
- ILO_DEV_ASSERT(r->dev, 6, 6);
-
- gen6_PIPE_CONTROL(r->builder, dw1, bo, 0, 0);
-
- r->state.current_pipe_control_dw1 |= dw1;
-
- assert(!r->state.deferred_pipe_control_dw1);
-}
-
static void
gen6_3dprimitive(struct ilo_render *r,
const struct pipe_draw_info *info,
@@ -120,14 +102,14 @@ gen6_wa_pre_pipe_control(struct ilo_render *r, uint32_t dw1)
const uint32_t direct_wa = GEN6_PIPE_CONTROL_CS_STALL |
GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
- gen6_pipe_control(r, direct_wa);
+ ilo_render_pipe_control(r, direct_wa);
}
if (indirect_wa_cond &&
!(r->state.current_pipe_control_dw1 & GEN6_PIPE_CONTROL_WRITE__MASK)) {
const uint32_t indirect_wa = GEN6_PIPE_CONTROL_WRITE_IMM;
- gen6_pipe_control(r, indirect_wa);
+ ilo_render_pipe_control(r, indirect_wa);
}
}
@@ -158,7 +140,7 @@ gen6_wa_post_3dstate_constant_vs(struct ilo_render *r)
gen6_wa_pre_pipe_control(r, dw1);
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
static void
@@ -178,7 +160,7 @@ gen6_wa_pre_3dstate_wm_max_threads(struct ilo_render *r)
gen6_wa_pre_pipe_control(r, dw1);
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
static void
@@ -200,7 +182,7 @@ gen6_wa_pre_3dstate_multisample(struct ilo_render *r)
gen6_wa_pre_pipe_control(r, dw1);
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen6_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
static void
@@ -226,9 +208,9 @@ gen6_wa_pre_depth(struct ilo_render *r)
gen6_wa_pre_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL |
GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- gen6_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
- gen6_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- gen6_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
}
#define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
diff --git a/src/gallium/drivers/ilo/ilo_render_gen7.c b/src/gallium/drivers/ilo/ilo_render_gen7.c
index 2d3f6cf..a8a222d 100644
--- a/src/gallium/drivers/ilo/ilo_render_gen7.c
+++ b/src/gallium/drivers/ilo/ilo_render_gen7.c
@@ -35,34 +35,6 @@
#include "ilo_state.h"
#include "ilo_render_gen.h"
-/**
- * A wrapper for gen6_PIPE_CONTROL().
- */
-static void
-gen7_pipe_control(struct ilo_render *r, uint32_t dw1)
-{
- struct intel_bo *bo = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) ?
- r->workaround_bo : NULL;
-
- ILO_DEV_ASSERT(r->dev, 7, 7.5);
-
- if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
- /* CS stall cannot be set alone */
- const uint32_t mask = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
- GEN6_PIPE_CONTROL_DEPTH_STALL |
- GEN6_PIPE_CONTROL_WRITE__MASK;
- if (!(dw1 & mask))
- dw1 |= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
- }
-
- gen6_PIPE_CONTROL(r->builder, dw1, bo, 0, 0);
-
- r->state.current_pipe_control_dw1 |= dw1;
- r->state.deferred_pipe_control_dw1 &= ~dw1;
-}
-
static void
gen7_3dprimitive(struct ilo_render *r,
const struct pipe_draw_info *info,
@@ -71,7 +43,7 @@ gen7_3dprimitive(struct ilo_render *r,
ILO_DEV_ASSERT(r->dev, 7, 7.5);
if (r->state.deferred_pipe_control_dw1)
- gen7_pipe_control(r, r->state.deferred_pipe_control_dw1);
+ ilo_render_pipe_control(r, r->state.deferred_pipe_control_dw1);
/* 3DPRIMITIVE */
gen7_3DPRIMITIVE(r->builder, info, ib);
@@ -115,7 +87,7 @@ gen7_wa_pre_vs(struct ilo_render *r)
ILO_DEV_ASSERT(r->dev, 7, 7);
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen7_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
static void
@@ -133,7 +105,7 @@ gen7_wa_pre_3dstate_sf_depth_bias(struct ilo_render *r)
ILO_DEV_ASSERT(r->dev, 7, 7);
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen7_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
static void
@@ -153,7 +125,7 @@ gen7_wa_pre_3dstate_multisample(struct ilo_render *r)
ILO_DEV_ASSERT(r->dev, 7, 7.5);
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen7_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
static void
@@ -174,7 +146,7 @@ gen7_wa_pre_depth(struct ilo_render *r)
GEN6_PIPE_CONTROL_WRITE_IMM;
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen7_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
/*
@@ -190,9 +162,9 @@ gen7_wa_pre_depth(struct ilo_render *r)
* guarantee that the pipeline from WM onwards is already flushed
* (e.g., via a preceding MI_FLUSH)."
*/
- gen7_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
- gen7_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- gen7_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
}
static void
@@ -210,7 +182,7 @@ gen7_wa_pre_3dstate_ps_max_threads(struct ilo_render *r)
ILO_DEV_ASSERT(r->dev, 7, 7.5);
if ((r->state.current_pipe_control_dw1 & dw1) != dw1)
- gen7_pipe_control(r, dw1);
+ ilo_render_pipe_control(r, dw1);
}
static void
diff --git a/src/gallium/drivers/ilo/ilo_render_gen8.c b/src/gallium/drivers/ilo/ilo_render_gen8.c
index 36fc129..49c5e7a 100644
--- a/src/gallium/drivers/ilo/ilo_render_gen8.c
+++ b/src/gallium/drivers/ilo/ilo_render_gen8.c
@@ -35,35 +35,6 @@
#include "ilo_state.h"
#include "ilo_render_gen.h"
-/**
- * A wrapper for gen6_PIPE_CONTROL().
- */
-static void
-gen8_pipe_control(struct ilo_render *r, uint32_t dw1)
-{
- struct intel_bo *bo = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK) ?
- r->workaround_bo : NULL;
-
- ILO_DEV_ASSERT(r->dev, 8, 8);
-
- if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
- /* CS stall cannot be set alone */
- const uint32_t mask = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
- GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
- GEN6_PIPE_CONTROL_DEPTH_STALL |
- GEN6_PIPE_CONTROL_WRITE__MASK;
- if (!(dw1 & mask))
- dw1 |= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
- }
-
- gen6_PIPE_CONTROL(r->builder, dw1, bo, 0, 0);
-
-
- r->state.current_pipe_control_dw1 |= dw1;
- r->state.deferred_pipe_control_dw1 &= ~dw1;
-}
-
static void
gen8_3dprimitive(struct ilo_render *r,
const struct pipe_draw_info *info,
@@ -72,7 +43,7 @@ gen8_3dprimitive(struct ilo_render *r,
ILO_DEV_ASSERT(r->dev, 8, 8);
if (r->state.deferred_pipe_control_dw1)
- gen8_pipe_control(r, r->state.deferred_pipe_control_dw1);
+ ilo_render_pipe_control(r, r->state.deferred_pipe_control_dw1);
/* 3DPRIMITIVE */
gen7_3DPRIMITIVE(r->builder, info, ib);
@@ -99,9 +70,9 @@ gen8_wa_pre_depth(struct ilo_render *r)
* guarantee that the pipeline from WM onwards is already flushed
* (e.g., via a preceding MI_FLUSH)."
*/
- gen8_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
- gen8_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
- gen8_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_DEPTH_STALL);
}
#define DIRTY(state) (session->pipe_dirty & ILO_DIRTY_ ## state)
@@ -461,7 +432,7 @@ ilo_render_emit_rectlist_commands_gen8(struct ilo_render *r,
gen8_3DSTATE_WM_HZ_OP(r->builder, op, blitter->fb.width,
blitter->fb.height, blitter->fb.num_samples);
- gen8_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
+ ilo_render_pipe_control(r, GEN6_PIPE_CONTROL_WRITE_IMM);
gen8_disable_3DSTATE_WM_HZ_OP(r->builder);
}
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