Mesa (master): i965/fs: Set smear on shader_time diff register.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: f1adc45dbe649cdd4538fb96f6d2a27328bbfba1
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1adc45dbe649cdd4538fb96f6d2a27328bbfba1

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Sun Mar  8 00:13:41 2015 -0800

i965/fs: Set smear on shader_time diff register.

The ADD(diff, diff, fs_reg(-2u)) instruction reads diff, which is a
width 1 register.  We need to read it as <0,1,0> with a subreg of 0,
which is what smear accomplishes.

Fixes assertion:
brw_eu_emit.c:285: validate_reg: Assertion `hstride == 0' failed.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86974
Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Matt Turner <mattst88 at gmail.com>
Cc: mesa-stable at lists.freedesktop.org

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |    1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 951cd97..71087f2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -765,6 +765,7 @@ fs_visitor::emit_shader_time_end()
    fs_reg start = shader_start_time;
    start.negate = true;
    fs_reg diff = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD, 1);
+   diff.set_smear(0);
    fs_inst *add = ADD(diff, start, shader_end_time);
    add->force_writemask_all = true;
    emit(add);