Mesa (master): i965/skl: Disable partial resolve in VC

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: 9d32d358500733249d3c0264c7458c2e5a65f515
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d32d358500733249d3c0264c7458c2e5a65f515

Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Thu Feb 26 18:14:17 2015 -0800

i965/skl: Disable partial resolve in VC

Recomendation [sic] is to set this field to 1 always. Programming it to default
value of 0, may have -ve impact on performance for MSAA WLs.

Another don't suck bit which needs to get set.

The patch wasn't as well tested as I would have liked, primarily I don't have
perf numbers for it, but it's getting to a point where it is in danger of being
lost.

v2: v1 was a mix of two patches. Since 0x7004 is masked, we only need to set it
once at initialization and make sure the pma workaround doesn't set the mask bit
(which it doesn't).
Move LRI to init gpu state (Ken)
Add a comment.

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>

---

 src/mesa/drivers/dri/i965/brw_state_upload.c |   10 ++++++++++
 src/mesa/drivers/dri/i965/intel_reg.h        |    1 +
 2 files changed, 11 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 1b84859..e446de6 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -337,6 +337,16 @@ brw_upload_initial_gpu_state(struct brw_context *brw)
 
    brw_upload_invariant_state(brw);
 
+   /* Recommended optimization for Victim Cache eviction in pixel backend. */
+   if (brw->gen >= 9) {
+      BEGIN_BATCH(3);
+      OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2));
+      OUT_BATCH(GEN7_CACHE_MODE_1);
+      OUT_BATCH((GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC << 16) |
+                GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC);
+      ADVANCE_BATCH();
+   }
+
    if (brw->gen >= 8) {
       gen8_emit_3dstate_sample_pattern(brw);
    }
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h b/src/mesa/drivers/dri/i965/intel_reg.h
index e5730e2..488fb5b 100644
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@ -144,5 +144,6 @@
 #define GEN7_CACHE_MODE_1               0x7004
 # define GEN8_HIZ_NP_PMA_FIX_ENABLE        (1 << 11)
 # define GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE (1 << 13)
+# define GEN9_PARTIAL_RESOLVE_DISABLE_IN_VC (1 << 1)
 # define GEN8_HIZ_PMA_MASK_BITS \
    ((GEN8_HIZ_NP_PMA_FIX_ENABLE | GEN8_HIZ_NP_EARLY_Z_FAILS_DISABLE) << 16)