Mesa (master): i965: Set MaxCombinedUniformBlocks properly.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 292df1940126f267418e656b9ec33eb3f06667b8
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=292df1940126f267418e656b9ec33eb3f06667b8

Author: Kenneth Graunke <kenneth at whitecape.org>
Date:   Fri Nov 13 14:55:50 2015 -0800

i965: Set MaxCombinedUniformBlocks properly.

Up until now, we've been letting core Mesa initialize it to 36 for us
(which is presumably BRW_MAX_UBO (12) * (VS+GS+FS stages -> 3)).

With compute and tessellation, we need to increase this.

Signed-off-by: Kenneth Graunke <kenneth at whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

---

 src/mesa/drivers/dri/i965/brw_context.c |    1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c
index e70ad98..2ea0a9e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -391,6 +391,7 @@ brw_initialize_context_constants(struct brw_context *brw)
            ctx->Const.Program[MESA_SHADER_FRAGMENT].MaxTextureImageUnits);
 
    ctx->Const.MaxUniformBufferBindings = num_stages * BRW_MAX_UBO;
+   ctx->Const.MaxCombinedUniformBlocks = num_stages * BRW_MAX_UBO;
    ctx->Const.MaxCombinedAtomicBuffers = num_stages * BRW_MAX_ABO;
    ctx->Const.MaxCombinedShaderStorageBlocks = num_stages * BRW_MAX_SSBO;
    ctx->Const.MaxShaderStorageBufferBindings = num_stages * BRW_MAX_SSBO;