Mesa (master): mesa: Add missing _mm_mfence() before streaming loads.

[Matt Turner]

Module: Mesa
Branch: master
Commit: 36ea9922ada5ea99e54231697a4afb31d5f6b9bf
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=36ea9922ada5ea99e54231697a4afb31d5f6b9bf

Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu Oct  1 10:06:55 2015 -0700

mesa: Add missing _mm_mfence() before streaming loads.

According to the Intel Software Development Manual (Volume 1: Basic
Architecture, 12.10.3 Streaming Load Hint Instruction):

   Streaming loads may be weakly ordered and may appear to software to
   execute out of order with respect to other memory operations.
   Software must explicitly use fences (e.g. MFENCE) if it needs to
   preserve order among streaming loads or between streaming loads and
   other memory operations.

That is, a memory fence is needed to preserve the order between the GPU
writing the buffer and the streaming loads reading it back.

Reported-by: Joseph Nuzman <joseph.nuzman at intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>

---

 src/mesa/main/streaming-load-memcpy.c |    3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/streaming-load-memcpy.c b/src/mesa/main/streaming-load-memcpy.c
index d7147af..32854b6 100644
--- a/src/mesa/main/streaming-load-memcpy.c
+++ b/src/mesa/main/streaming-load-memcpy.c
@@ -59,6 +59,9 @@ _mesa_streaming_load_memcpy(void *restrict dst, void *restrict src, size_t len)
       len -= MIN2(bytes_before_alignment_boundary, len);
    }
 
+   if (len >= 64)
+      _mm_mfence();
+
    while (len >= 64) {
       __m128i *dst_cacheline = (__m128i *)d;
       __m128i *src_cacheline = (__m128i *)s;