Mesa (master): i965/gen9: Handle the GL_TEXTURE_{1D, 1D_ARRAY} targets inside switch

[Anuj Phogat]

Module: Mesa
Branch: master
Commit: 2eed9e6b756d1e0232ad749cb89e97d535e141bd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eed9e6b756d1e0232ad749cb89e97d535e141bd

Author: Anuj Phogat <anuj.phogat at gmail.com>
Date:   Wed Aug 12 11:34:54 2015 -0700

i965/gen9: Handle the GL_TEXTURE_{1D, 1D_ARRAY} targets inside switch

Signed-off-by: Anuj Phogat <anuj.phogat at gmail.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

---

 src/mesa/drivers/dri/i965/brw_tex_layout.c |    8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 2955c8d..67628c9 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -162,9 +162,7 @@ tr_mode_vertical_texture_alignment(const struct brw_context *brw,
    const unsigned align_3d_ys[] = {32, 32, 32, 16, 16};
    int i = 0;
 
-   assert(brw->gen >= 9 &&
-          mt->target != GL_TEXTURE_1D &&
-          mt->target != GL_TEXTURE_1D_ARRAY);
+   assert(brw->gen >= 9);
 
    /* Alignment computations below assume bpp >= 8 and a power of 2. */
    assert (bpp >= 8 && bpp <= 128 && _mesa_is_pow_two(bpp)) ;
@@ -184,8 +182,10 @@ tr_mode_vertical_texture_alignment(const struct brw_context *brw,
       align_yf = align_3d_yf;
       align_ys = align_3d_ys;
       break;
+   case GL_TEXTURE_1D:
+   case GL_TEXTURE_1D_ARRAY:
    default:
-      unreachable("not reached");
+      unreachable("Unexpected miptree target");
    }
 
    /* Compute array index. */