Mesa (master): i965/gen8+: Skip depth stalls on state change

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: e8a219ab463a0071f4d9c5d88feeeaa87b2a01f2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8a219ab463a0071f4d9c5d88feeeaa87b2a01f2

Author: Ben Widawsky <benjamin.widawsky at intel.com>
Date:   Wed Aug 26 10:52:58 2015 -0700

i965/gen8+: Skip depth stalls on state change

Docs suggest this is no longer required starting with Gen8.

Perf (no regressions in n=20)
OglMultithread       0.67%
OglTerrainPanInst    0.12%
trex                 0.45%
warsow               0.64%

Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

---

 src/mesa/drivers/dri/i965/brw_pipe_control.c |    8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 7ee3cb6..a2aef8a 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -193,6 +193,14 @@ brw_emit_depth_stall_flushes(struct brw_context *brw)
 {
    assert(brw->gen >= 6 && brw->gen <= 9);
 
+   /* Starting on BDW, these pipe controls are unnecessary.
+    *
+    *   WM HW will internally manage the draining pipe and flushing of the caches
+    *   when this command is issued. The PIPE_CONTROL restrictions are removed.
+    */
+   if (brw->gen >= 8)
+      return;
+
    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
    brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);