Mesa (master): nvc0: add hardware ETC2 and ASTC support on GK20A and GM107+
Ilia Mirkin
imirkin at kemper.freedesktop.org
Mon Apr 4 04:37:30 UTC 2016
Module: Mesa
Branch: master
Commit: 4bc3b1ca487df6072aec13dbfbf724c0de9995c5
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bc3b1ca487df6072aec13dbfbf724c0de9995c5
Author: Ilia Mirkin <imirkin at alum.mit.edu>
Date: Sun Apr 3 14:13:33 2016 -0400
nvc0: add hardware ETC2 and ASTC support on GK20A and GM107+
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/gallium/drivers/nouveau/nv50/nv50_formats.c | 46 +++++++++++++++++++++++++
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 13 +++++++
src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 7 ++--
3 files changed, 64 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index 717067c..5b96567 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -23,6 +23,7 @@
#if NOUVEAU_DRIVER == 0xc0
# include "nvc0/nvc0_screen.h"
# include "nvc0/nvc0_3d.xml.h"
+# include "nvc0/gm107_texture.xml.h"
#else
# include "nv50/nv50_screen.h"
# include "nv50/nv50_3d.xml.h"
@@ -65,6 +66,7 @@
#define SF_A(sz) G80_TIC_0_COMPONENTS_SIZES_##sz
#define SF_B(sz) G200_TIC_0_COMPONENTS_SIZES_##sz
#define SF_C(sz) GF100_TIC_0_COMPONENTS_SIZES_##sz
+#define SF_D(sz) GM107_TIC2_0_COMPONENTS_SIZES_##sz
#define SF(c, pf, sf, r, g, b, a, t0, t1, t2, t3, sz, u) \
[PIPE_FORMAT_##pf] = { \
sf, { \
@@ -236,6 +238,50 @@ const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
F3(C, BPTC_RGB_FLOAT, NONE, R, G, B, xx, FLOAT, BC6H_SF16, t),
F3(C, BPTC_RGB_UFLOAT, NONE, R, G, B, xx, FLOAT, BC6H_UF16, t),
+#if NOUVEAU_DRIVER == 0xc0
+ F3(D, ETC1_RGB8, NONE, R, G, B, xx, UNORM, ETC2_RGB, t),
+ F3(D, ETC2_RGB8, NONE, R, G, B, xx, UNORM, ETC2_RGB, t),
+ F3(D, ETC2_SRGB8, NONE, R, G, B, xx, UNORM, ETC2_RGB, t),
+ C4(D, ETC2_RGB8A1, NONE, R, G, B, A, UNORM, ETC2_RGB_PTA, t),
+ C4(D, ETC2_SRGB8A1, NONE, R, G, B, A, UNORM, ETC2_RGB_PTA, t),
+ C4(D, ETC2_RGBA8, NONE, R, G, B, A, UNORM, ETC2_RGBA, t),
+ C4(D, ETC2_SRGBA8, NONE, R, G, B, A, UNORM, ETC2_RGBA, t),
+ F1(D, ETC2_R11_UNORM, NONE, R, xx, xx, xx, UNORM, EAC, t),
+ F1(D, ETC2_R11_SNORM, NONE, R, xx, xx, xx, SNORM, EAC, t),
+ F2(D, ETC2_RG11_UNORM, NONE, R, G, xx, xx, UNORM, EACX2, t),
+ F2(D, ETC2_RG11_SNORM, NONE, R, G, xx, xx, SNORM, EACX2, t),
+
+ C4(D, ASTC_4x4, NONE, R, G, B, A, UNORM, ASTC_2D_4X4, t),
+ C4(D, ASTC_5x4, NONE, R, G, B, A, UNORM, ASTC_2D_5X4, t),
+ C4(D, ASTC_5x5, NONE, R, G, B, A, UNORM, ASTC_2D_5X5, t),
+ C4(D, ASTC_6x5, NONE, R, G, B, A, UNORM, ASTC_2D_6X5, t),
+ C4(D, ASTC_6x6, NONE, R, G, B, A, UNORM, ASTC_2D_6X6, t),
+ C4(D, ASTC_8x5, NONE, R, G, B, A, UNORM, ASTC_2D_8X5, t),
+ C4(D, ASTC_8x6, NONE, R, G, B, A, UNORM, ASTC_2D_8X6, t),
+ C4(D, ASTC_8x8, NONE, R, G, B, A, UNORM, ASTC_2D_8X8, t),
+ C4(D, ASTC_10x5, NONE, R, G, B, A, UNORM, ASTC_2D_10X5, t),
+ C4(D, ASTC_10x6, NONE, R, G, B, A, UNORM, ASTC_2D_10X6, t),
+ C4(D, ASTC_10x8, NONE, R, G, B, A, UNORM, ASTC_2D_10X8, t),
+ C4(D, ASTC_10x10, NONE, R, G, B, A, UNORM, ASTC_2D_10X10, t),
+ C4(D, ASTC_12x10, NONE, R, G, B, A, UNORM, ASTC_2D_12X10, t),
+ C4(D, ASTC_12x12, NONE, R, G, B, A, UNORM, ASTC_2D_12X12, t),
+
+ C4(D, ASTC_4x4_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_4X4, t),
+ C4(D, ASTC_5x4_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_5X4, t),
+ C4(D, ASTC_5x5_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_5X5, t),
+ C4(D, ASTC_6x5_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_6X5, t),
+ C4(D, ASTC_6x6_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_6X6, t),
+ C4(D, ASTC_8x5_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_8X5, t),
+ C4(D, ASTC_8x6_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_8X6, t),
+ C4(D, ASTC_8x8_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_8X8, t),
+ C4(D, ASTC_10x5_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_10X5, t),
+ C4(D, ASTC_10x6_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_10X6, t),
+ C4(D, ASTC_10x8_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_10X8, t),
+ C4(D, ASTC_10x10_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_10X10, t),
+ C4(D, ASTC_12x10_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_12X10, t),
+ C4(D, ASTC_12x12_SRGB, NONE, R, G, B, A, UNORM, ASTC_2D_12X12, t),
+#endif
+
C4(A, R32G32B32A32_FLOAT, RGBA32_FLOAT, R, G, B, A, FLOAT, R32_G32_B32_A32, IB),
C4(A, R32G32B32A32_UNORM, NONE, R, G, B, A, UNORM, R32_G32_B32_A32, T),
C4(A, R32G32B32A32_SNORM, NONE, R, G, B, A, SNORM, R32_G32_B32_A32, T),
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
index 14438ce..ec2340e 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c
@@ -45,6 +45,8 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
unsigned sample_count,
unsigned bindings)
{
+ const struct util_format_description *desc = util_format_description(format);
+
if (sample_count > 8)
return false;
if (!(0x117 & (1 << sample_count))) /* 0, 1, 2, 4 or 8 */
@@ -65,6 +67,17 @@ nvc0_screen_is_format_supported(struct pipe_screen *pscreen,
sample_count > 1)
return false;
+ /* Restrict ETC2 and ASTC formats here. These are only supported on GK20A.
+ */
+ if ((desc->layout == UTIL_FORMAT_LAYOUT_ETC ||
+ desc->layout == UTIL_FORMAT_LAYOUT_ASTC) &&
+ /* The claim is that this should work on GM107 but it doesn't. Need to
+ * test further and figure out if it's a nouveau issue or a HW one.
+ nouveau_screen(pscreen)->class_3d < GM107_3D_CLASS &&
+ */
+ nouveau_screen(pscreen)->class_3d != NVEA_3D_CLASS)
+ return false;
+
/* transfers & shared are always supported */
bindings &= ~(PIPE_BIND_TRANSFER_READ |
PIPE_BIND_TRANSFER_WRITE |
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
index ce6a6dc..e04573f 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c
@@ -250,6 +250,7 @@ gf100_create_texture_view(struct pipe_context *pipe,
uint32_t swz[4];
uint32_t width, height;
uint32_t depth;
+ uint32_t tex_fmt;
struct nv50_tic_entry *view;
struct nv50_miptree *mt;
bool tex_int;
@@ -275,12 +276,13 @@ gf100_create_texture_view(struct pipe_context *pipe,
fmt = &nvc0_format_table[view->pipe.format];
tex_int = util_format_is_pure_integer(view->pipe.format);
+ tex_fmt = fmt->tic.format & 0x3f;
swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
- tic[0] = (fmt->tic.format << G80_TIC_0_COMPONENTS_SIZES__SHIFT) |
+ tic[0] = (tex_fmt << G80_TIC_0_COMPONENTS_SIZES__SHIFT) |
(fmt->tic.type_r << G80_TIC_0_R_DATA_TYPE__SHIFT) |
(fmt->tic.type_g << G80_TIC_0_G_DATA_TYPE__SHIFT) |
(fmt->tic.type_b << G80_TIC_0_B_DATA_TYPE__SHIFT) |
@@ -288,7 +290,8 @@ gf100_create_texture_view(struct pipe_context *pipe,
(swz[0] << G80_TIC_0_X_SOURCE__SHIFT) |
(swz[1] << G80_TIC_0_Y_SOURCE__SHIFT) |
(swz[2] << G80_TIC_0_Z_SOURCE__SHIFT) |
- (swz[3] << G80_TIC_0_W_SOURCE__SHIFT);
+ (swz[3] << G80_TIC_0_W_SOURCE__SHIFT) |
+ ((fmt->tic.format & 0x40) << (GK20A_TIC_0_USE_COMPONENT_SIZES_EXTENDED__SHIFT - 6));
address = mt->base.address;
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