Mesa (master): radeonsi: don't flush CB/DB caches for performance counters

Marek Olšák mareko at kemper.freedesktop.org
Mon Apr 18 17:51:40 UTC 2016


Module: Mesa
Branch: master
Commit: 28c2573b4f1b311145b3f21a1794adb3dcd5f61a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=28c2573b4f1b311145b3f21a1794adb3dcd5f61a

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sun Apr 17 15:18:31 2016 +0200

radeonsi: don't flush CB/DB caches for performance counters

I'm not sure about this. This will make the engines go idle, but the caches
will be unflushed. This should match app behavior without performance
counters, which can be a good thing.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

---

 src/gallium/drivers/radeonsi/si_perfcounter.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_perfcounter.c b/src/gallium/drivers/radeonsi/si_perfcounter.c
index 24855e4..04da197 100644
--- a/src/gallium/drivers/radeonsi/si_perfcounter.c
+++ b/src/gallium/drivers/radeonsi/si_perfcounter.c
@@ -591,9 +591,12 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
 	struct radeon_winsys_cs *cs = ctx->gfx.cs;
 
 	if (ctx->screen->chip_class == CIK) {
-		/* Workaround for cache flush problems: send two EOP events. */
+		/* Two EOP events are required to make all engines go idle
+		 * (and optional cache flushes executed) before the timestamp
+		 * is written.
+		 */
 		radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) |
+		radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
 				EVENT_INDEX(5));
 		radeon_emit(cs, va);
 		radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
@@ -602,7 +605,7 @@ static void si_pc_emit_stop(struct r600_common_context *ctx,
 	}
 
 	radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
-	radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) |
+	radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_BOTTOM_OF_PIPE_TS) |
 			EVENT_INDEX(5));
 	radeon_emit(cs, va);
 	radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));




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