Mesa (master): 34 new commits

Tue Apr 19 16:32:31 UTC 2016

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=464cef5b06e65aa740704e4adac68b7f5fee1b88
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Mar 19 15:16:50 2016 +0100

    radeonsi: enable TGSI support cap for compute shaders
    
    v2: Use chip_class instead of family.
    
    v3: Check kernel version for SI.
    
    v4: Preemptively allow amdgpu winsys for SI.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f32d5d59fff7a4ef42cd2811ef4116c5827b9a0
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Apr 19 14:08:13 2016 +0200

    radeonsi: Consider input SGPR count for compute shader SGPR count.
    
    si_shader_create corrects the SGPR count with si_fix_num_sgprs. We then
    recompute the rsrc1 register to use the new SGPR count.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c833ba1ab7ffe615d8c025a7452984083c1143b
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Apr 19 13:52:32 2016 +0200

    radeonsi: Add CE synchronization for compute dispatches.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0b729c544ab0f25cd90af5daffdff0940743e14
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Apr 2 13:39:54 2016 +0200

    mesa/st: enable compute shaders if images are also supported
    
    v2: Also depend on atomic counters.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=41d79bcbfa64f6f72b0090e12838073983ea6e5b
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Apr 2 11:37:06 2016 +0200

    radeonsi: clean up compute flush
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a92c0842892bf55a82b7d95ab5a3b7dfbb83407
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sun Mar 27 11:14:34 2016 +0200

    radeonsi: do not do two full flushes on every compute dispatch
    
    v2: Add more CS_PARTIAL_FLUSH events.
    
    Essentially every place with waits on finishing for pixel shaders
    also has a write after read hazard with compute shaders.
    
    Invalidating L2 waits implicitly on pixel and compute shaders,
    so, we don't need a CS_PARTIAL_FLUSH for switching FBO.
    
    v3: Add CS_PARTIAL_FLUSH events even if we already have INV_GLOBAL_L2.
    
    According to Marek the INV_GLOBAL_L2 events don't wait for compute
    shaders to finish, so wait for them explicitly.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e764ee13ae21e3c1dbda24daeb2d08c5e7c81871
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Mar 19 13:56:29 2016 +0100

    radeonsi: split setting graphics and compute descriptors
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=061ce9399a08f3edd4f5af16afd36bb14d58c864
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Mar 19 18:41:20 2016 +0100

    radeonsi: split texture decompression for compute shaders
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e56514f6316e48ee2231841d45695ff2b8f8b4f5
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Apr 5 17:38:38 2016 +0200

    radeonsi: update predicate condition for compute dispatches
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3083d841e04e14d3682e55cf5d1004f5310e9d4
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Mar 19 15:15:20 2016 +0100

    radeonsi: implement TGSI compute dispatch
    
    v2: - Use radeon_set_sh_reg_seq.
        - Set predicate bit for conditional rendering.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1349dd16ff4f0e40e9ecefcb818302752cd0bf38
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Apr 2 13:19:42 2016 +0200

    radeonsi: only emit compute shader state when switching shaders
    
    v2: - Do check if anything changed earlier
        - Use emitted_program instead of emitted_bo to prevent
          shaders with shader->bo = NULL confusing the check
        - Use radeon_set_sh_reg*
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba1f66a73d493c49a3a329d9f3882ddbae4147b0
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Apr 2 13:04:18 2016 +0200

    radeonsi: rework compute scratch buffer
    
    Instead of having a scratch buffer per program, have one per
    context.
    
    Also removed the per kernel wave count calculations, but
    that only helped if the total number of waves in the dispatch
    was smaller than sctx->scratch_waves.
    
    v2: Fix style issue.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=107f4d3538e6eeab396bf41a4d4334950adf81ac
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Apr 2 12:35:36 2016 +0200

    radeonsi: do per cs setup for compute shaders once per cs
    
    Also removes PKT3_CONTEXT_CONTROL as that is already being done
    by si_begin_new_cs, when emitting init_config.
    
    v2: - Use radeon_set_sh_reg_seq.
        - Also set COMPUTE_STATIC_THREAD_MGMT_SE2 / SE3 for CIK+
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=52d3584decfa00f3f96633edd7f2b6c4a0febabf
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Apr 2 12:48:05 2016 +0200

    radeonsi: don't pass scratch buffer to user SGPRs
    
    As far as I can see we use relocations for clover too.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=422a19f76fce5a308f380d02b54e426ebd7aa87f
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Apr 2 12:04:15 2016 +0200

    radeonsi: split input upload off from si_launch_grid
    
    Also uses a dynamically allocated buffer using u_upload_alloc.
    The old buffer per program approach required serializing all
    dispatches of the same program.
    
    v2: - Clarified commit message.
        - Use radeon_set_sh_reg_seq.
        - Also upload input buffer for clover kernels, even when
          input_size is 0, as it contains grid parameters.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=898298efc93ea873b6e537fda028508349d41628
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Mar 19 14:07:33 2016 +0100

    radeonsi: implement TGSI compute shader creation
    
    v2: Moved scratch_enabled initialization after compile.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=85fd7817eef4639ad69ad27807827f335f8b3ed0
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sat Mar 19 13:54:55 2016 +0100

    radeonsi: update shader count for compute shaders
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=da88c2a8e85350875aa60ef9cd2442666b2109ec
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Mon Mar 28 03:01:56 2016 +0200

    radeonsi: set maximum work group size based on block size
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b082147b788ee45862f8d1b0e1b47478d6b99447
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Mar 29 13:20:26 2016 +0200

    radeonsi: implement shared atomics
    
    v2: - Use single region
        - Use get_memory_ptr
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8acf3e501b40aa30371105c18187441085369dfe
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Mar 29 13:17:40 2016 +0200

    radeonsi: implement shared memory load/store
    
    v2: - Use single region
        - Combine address calculation
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=84a6761ae34105fbdb38757a07e229b2392545d3
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Tue Mar 29 17:51:49 2016 +0200

    radeonsi: add shared memory
    
    Declares the shared memory as a global variable so that
    LLVM is aware of it and it does not conflict with passes
    like AMDGPUPromoteAlloca.
    
    v2: - Use ctx->i8.
        - Dropped null-check for declare_memory_region.
        - Changed memory region array to single region.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>
    Reviewed-by: Edward O'Callaghan <eocallaghan at alterapraxis.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=753a3e472b4c026d96f9984b02b53f596a0d595e
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu Mar 17 14:12:21 2016 +0100

    radeonsi: lower compute shader arguments
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>
    Reviewed-by: Nicolai Hähnle <nicolai.haehnle at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=008d977d01255cca50fd222caea04f6787cb3b59
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu Mar 10 21:39:20 2016 +0100

    radeonsi: Use CE for all descriptors.
    
    v2: Load previous list for new CS instead of re-emitting
        all descriptors.
    
    v3: Do radeon_add_to_buffer_list in si_ce_upload.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b6c463dac4a25c927f419e65023979cc45ce60d
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Wed Apr 13 23:30:55 2016 +0200

    gallium/util: Add u_bit_scan_consecutive_range64.
    
    For use by radeonsi.
    
    v2: Make sure that it works for all 64 bits set.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=058b54c6244416e47ec211e2300624cd9e3ae623
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Fri Apr 15 01:00:41 2016 +0200

    radeonsi: Replace list_dirty with a mask.
    
    We can then upload only the dirty ones with the constant engine.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aabc7d61d6826164f5ecf8243a6265af6c6ee62c
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu Mar 10 21:23:49 2016 +0100

    radeonsi: Add CE uploader.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d7ddd6819b1007ee1490755068660fbc436e974
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu Mar 10 21:19:37 2016 +0100

    radeonsi: Allocate chunks of CE ram.
    
    v2: Use 32 byte alignment.
    
    v3: Don't allocate CE space for vertex buffer descriptors.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=86c71ff989f39401e3a8195aabcaae8dae89146b
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu Mar 10 21:01:39 2016 +0100

    radeonsi: Add CE synchronization.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe1ef23b6698a55613bc7c4d46bd68aeff080d43
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu Mar 10 20:59:16 2016 +0100

    radeonsi: Add CE packet definitions.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fee75d606e83b1f0d665fef9ea59ba24fc6682d
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Wed Apr 13 22:31:17 2016 +0200

    radeonsi: Create CE IB.
    
    Based on work by Marek Olšák.
    
    v2: Add preamble IB.
    
    Leaves the load packet in the space calculation as the
    radeon winsys might not be able to support a premable.
    
    The added space calculation may look expensive, but
    is converted to a constant with (at least) -O2 and -O3.
    
    v3: - Fix code style.
        - Remove needed space for vertex buffer descriptors.
        - Fail when the preamble cannot be created.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7201230582e060aa2eb79c825d3188b437ef7bb8
Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Thu Apr 14 02:11:07 2016 +0200

    winsys/amdgpu: Enlarge const IB size.
    
    Necessary to prevent performance regressions due to extra flushing.
    
    Probably should enlarge it even further when also updating
    uniforms through the CE, but this seems large enough for now.
    
    v2: Add preamble IB.
    
    Signed-off-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7997b5f005d4051e84bf64d6d1294f3da5076e5a
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Aug 8 14:02:02 2015 +0200

    winsys/amdgpu: Add support for const IB.
    
    v2: Use the correct IB to update request (Bas Nieuwenhuizen)
    v3: Add preamble IB. (Bas Nieuwenhuizen)
    Reviewed-by: Marek Olšák <marek.olsak at amd.com>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e78170f388fdabf3b981839ae265632b974f5569
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Aug 8 13:27:38 2015 +0200

    winsys/amdgpu: split IB data into a new structure in preparation for CE
    
    Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4b77c764a2469b20cfe49ec3ea3cca8e49dea92
Author: Marek Olšák <marek.olsak at amd.com>
Date:   Sat Aug 8 14:12:10 2015 +0200

    gallium/radeon: move ring_type into winsyses
    
    Not used by drivers.
    
    Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>