Mesa (master): 36 new commits

Thu Apr 21 07:41:08 UTC 2016

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=935ce14a445f794cdccc749738353d76d0205145
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Apr 19 20:08:55 2016 +0300

    i965/blorp: Reduce the urb size requirement for vertex buffer
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=26fdb7e51e9f6b407ad8c635850ccffbd01876bc
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Apr 19 19:57:43 2016 +0300

    i965/blorp: Reduce the size of vertex buffer
    
    Previously the vertex buffer consisted of eight floats per vertex
    of which six where constants. These can be as easily provided by
    vertex fetcher as it is capable of filling vertex elements with
    constant one and zero. This reduces the size of the vertex buffer
    from 3 * 8 * 4 = 96 to 3 * 2 * 4 = 24 bytes.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ae360f098d88450f73f2b2176a6839ab593da2a
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 15 14:03:18 2016 +0300

    i965/blorp: Do not tricker urb re-configuration unnecessarily
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=69dfb7b2b7f2686f782414bc303f24f584f8f850
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 15 13:39:48 2016 +0300

    i965/blorp: Skip re-emitting urb config whenever possible
    
    Otherwise clearing with blorp will regress performance in some
    synthetic test cases.
    
    v2: Used vsize >= 2 instead of vsize > 0, and updated the comment.
        Review by Ken in one of the earlier patches revealed this.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7644e8ab6814554420b01a900643ba72bb09b2c9
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 15 10:43:05 2016 +0300

    i965/blorp: Prepare to switch from compute pipeline
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa322f8ae5be1bbb32ecdacb0984d79c242f4a95
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Apr 12 00:18:45 2016 +0300

    i965/blorp: Skip uploading state/options not needed for clears
    
    In case there is no source it means the program does a simple
    clear or a resolve. In such case there is no need to program
    sampling state or enable pixel kill in fragment shader.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=87d333f2fe9e0be458eeff21ea70087ba524e9fa
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 1 15:57:54 2016 +0300

    i965/blorp: Re-introduce clear programs
    
    This partially reverts 2f28a0dc23165123cf1e8b5942acad37878edd8a
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=69c364f2dcd65bb5b5e7fa075f40a2be9e45bff0
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Wed Apr 6 11:38:59 2016 +0300

    i965/meta: Move check for srgb into is_color_fast_clear_compatible()
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a696e75d87da4f40e7ae26cb7fc47421b841455
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Wed Apr 6 10:53:04 2016 +0300

    i965/meta: Expose check for fast clear compatibility
    
    Also add the additional render format check to the same utility.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a848ad68063a12eba40a555c8e990b16501ed0ca
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Mon Apr 4 21:05:58 2016 +0300

    i965/meta: Expose fast clear value setup
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb14a2fc782e040c2d09706b277b783b4f26697f
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Mon Apr 4 13:43:24 2016 +0300

    i965/meta: Expose non-fast clear rectangle calculation
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d79235e4ec68c72876f8afd5d472571d2e7f0e3
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Mon Apr 4 11:28:03 2016 +0300

    i965/meta: Expose resolve clear rectangle calculation
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2757d723dab3d0d4010f3c02b50670ba67fac7d2
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Sun Apr 3 22:10:14 2016 +0300

    i965/meta: Expose fast clear rectangle calculation
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ef957e783a3a98622011b0a02996ef23b43a70e
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Sun Apr 3 22:15:13 2016 +0300

    i965: Declare input to mcs alignment calculation constant
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c40b1efa700cb594e397fd9ab839aa89cbbb067a
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Sun Apr 3 21:38:24 2016 +0300

    i965/blorp: Switch the order of render and texture targets
    
    On gen8 color resolving won't work anymore if the target isn't
    the first entry in the binding table.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d062d79c39a6e9556411f58a7ea4126811f9ae4
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Apr 5 10:36:11 2016 +0300

    i965/blorp: Reduce scope for generator and its inputs
    
    Generator is only needed for getting the assembly.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c3de6b2d651e43d686085872b916a04f4444930
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Sun Apr 3 18:51:43 2016 +0300

    i965/blorp: Add support for disabling color blending
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=da5a477ce413e4355eb5d826d112459629087fb0
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 1 21:42:21 2016 +0300

    i965/blorp: Add support for setting fast clear operation
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7de72f728b32bcbe70e28adcc8733154794c0343
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Wed Mar 30 20:41:30 2016 +0300

    i965/blorp: Enable blits on gen8
    
    v2 (Ken): Moved switch cases for gen8/9 in texel_fetch() to
              earlier patch adding gen8/9 sampling support.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7ab4e0cc4e56a7830d407fd708e3ffa408d06d6
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Thu Apr 7 18:50:56 2016 +0300

    i965/blorp: Prepare stencil sampling for gen8
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=708453952b5e27af4e29cb0351de9a465459f742
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 1 12:01:23 2016 +0300

    i965/blorp: Add check for supported sample numbers
    
    v2 (Ken): Fix the condition on using meta for stencil blits:
              use_blorp -> !use_blorp
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e4d19372b1d7f6ab12ddab1929a53335d9cce06
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 8 10:22:37 2016 +0300

    i965/blorp: Add support for sampling 3D textures
    
    This patch adds additional MOV instruction for all blorp programs
    that use SHADER_OPCODE_TXF. Alternative is to augment blorp program
    key to tell if z-coordinate is needed, add condition to the blorp
    blit compiler and to produce a variant with and without the MOV.
    This seems a little overkill.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b33d63d77ab7835b5883140e54316e86e73888d
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Sat Apr 9 19:48:14 2016 +0300

    i965/blorp: Add support for source swizzle
    
    In order to support cases where gen9 uses RGBA format to back client
    requested RGB, one needs to have means to force alpha channel to one
    when user requested RGB surface is used as blit source.
    
    v2 (Ken): Use helper for constructing the swizzle (this should be
              changed to use brw_get_texture_swizzle() as a follow-up).
              Also calculate the swizzle for CopyTexSubImage.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=52e7008a5a3655c9bd0abf8bfeb5110a98723e57
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Mar 29 10:50:42 2016 +0300

    i965/blorp: Pipeline upload support for gen8
    
    v2 (Ken): Drop GEN8_RASTER_FRONT_WINDING_CCW in raster state
              Add emission of pma stall.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fda44137188b8b5bc93ef0434ab3899507ea245
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Thu Apr 21 10:12:46 2016 +0300

    i965/gen8: Expose pma stall emission
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b2332e3d11dc047e11bc84a4f8da45ccfb6013b
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Thu Apr 7 13:09:52 2016 +0300

    i965: Allow texture surface state setup to be used by blorp
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ad83d222b0a4c3be676ca8708a4a565888b34fd
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 1 11:21:03 2016 +0300

    i965/blorp: Prepare sampling for gen9
    
    v2 (Ken): Added switch cases for gen8/9 in texel_fetch(). These
              were wrongly introduced in blit-enabling patch.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=328ab6c268b4cf8744915b96be4a6f031dc81ef9
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Wed Mar 30 20:50:41 2016 +0300

    i965/blorp: Prepare render target write for gen8
    
    v2 (Ken): Use payload directly instead of retyping it into vec8.
              Drop the implied header, it isn't used for gen6+ anyway.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=135f00e666fdc505d8b3f68cd673cde736ea35ee
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Mar 6 14:21:25 2015 +0200

    i965/blorp/gen6: Prepare vertex buffer setup logic for gen8
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=395abb9c3b8b7b1a3e757e6dfee5b23cf9cf5753
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Sun Mar 1 22:38:59 2015 +0200

    i965/blorp/gen7: Expose state setup applicable to gen8
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ede09e672ae277aa78def69fe016a4be454b28ed
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Apr 15 10:12:20 2016 +0300

    i965/blorp: Use 8k chunk size for urb allocation
    
    Previously, we hardcoded "VS URB Starting Address" to 2 (in 8kB chunks),
    which meant VS URB data would start at an offset of 16kB.
    
    However, on Haswell GT3 and Gen8+, we allocate the first 32kB for the
    push constant region.  This means that the PS push constant and VS URB
    data regions overlap, which can lead to corruption.
    
    v2 (Ken): Better description of the change, and do not change vs_size
              from 2 to 1.
    
    Cc: mesa-stable at lists.freedesktop.org
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=e04b3cdf33f6fdb363c652e935d8a0b427ef6b15
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Fri Mar 6 15:55:02 2015 +0200

    i965/blorp/gen7: Prepare re-using for gen8
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1ddfa8512df62422db00281ce216eff7ec5706c
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Apr 12 09:27:00 2016 +0300

    i965/blorp: Let compiler calculate the vertex buffer size
    
    Currently the size is sizeof(float) times too large. One reserves
    GEN6_BLORP_VBO_SIZE many floats whereas GEN6_BLORP_VBO_SIZE stands
    for the size of vertex buffer in bytes.
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c526370ca9020ab2ca9ea533a8ccb2fe901fe78
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Mon Mar 2 11:29:05 2015 +0200

    i965/gen8: Expose state base address setup
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=9949103756c19f8cbd37fb0ffb5b135cd24725ad
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Tue Mar 29 11:36:23 2016 +0300

    i965/gen8: Expose surface state helpers
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f1d9f2879e81acb59102ef24dba68b0d3d3af66
Author: Topi Pohjolainen <topi.pohjolainen at intel.com>
Date:   Thu Mar 31 10:19:24 2016 +0300

    i965/gen9: Use correct size for DS_STATE
    
    Signed-off-by: Topi Pohjolainen <topi.pohjolainen at intel.com>
    Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>