Mesa (master): radeonsi: remove the shader parameter from si_set_ring_buffer

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 8cfc4cf76daaafba448c4ab3240dc313879c2b4f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cfc4cf76daaafba448c4ab3240dc313879c2b4f

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Apr 21 17:52:29 2016 +0200

radeonsi: remove the shader parameter from si_set_ring_buffer

not used anymore

this is a follow-up to the RW buffer cleanup.

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>

---

 src/gallium/drivers/radeonsi/si_descriptors.c   |  5 +----
 src/gallium/drivers/radeonsi/si_state.h         |  2 +-
 src/gallium/drivers/radeonsi/si_state_shaders.c | 19 +++++++++----------
 3 files changed, 11 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index e44201b..6926c6b 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -907,7 +907,7 @@ static void si_set_shader_buffers(struct pipe_context *ctx, unsigned shader,
 
 /* RING BUFFERS */
 
-void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
+void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 			struct pipe_resource *buffer,
 			unsigned stride, unsigned num_records,
 			bool add_tid, bool swizzle,
@@ -916,9 +916,6 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
 	struct si_context *sctx = (struct si_context *)ctx;
 	struct si_buffer_resources *buffers = &sctx->rw_buffers;
 
-	if (shader >= SI_NUM_SHADERS)
-		return;
-
 	/* The stride field in the resource descriptor has 14 bits */
 	assert(stride < (1 << 14));
 
diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index ef9f864..ed3a1fe 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -248,7 +248,7 @@ struct si_buffer_resources {
 
 /* si_descriptors.c */
 void si_ce_enable_loads(struct radeon_winsys_cs *ib);
-void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
+void si_set_ring_buffer(struct pipe_context *ctx, uint slot,
 			struct pipe_resource *buffer,
 			unsigned stride, unsigned num_records,
 			bool add_tid, bool swizzle,
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c
index d02ce8f..4fc0797 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1565,15 +1565,15 @@ static bool si_update_gs_ring_buffers(struct si_context *sctx)
 
 	/* Set ring bindings. */
 	if (sctx->esgs_ring) {
-		si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_ES_RING_ESGS,
+		si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
 				   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
 				   true, true, 4, 64, 0);
-		si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_ESGS,
+		si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
 				   sctx->esgs_ring, 0, sctx->esgs_ring->width0,
 				   false, false, 0, 0, 0);
 	}
 	if (sctx->gsvs_ring)
-		si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_VS_RING_GSVS,
+		si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
 				   sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
 				   false, false, 0, 0, 0);
 	return true;
@@ -1589,22 +1589,22 @@ static void si_update_gsvs_ring_bindings(struct si_context *sctx)
 
 	sctx->last_gsvs_itemsize = gsvs_itemsize;
 
-	si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS0,
+	si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
 			   sctx->gsvs_ring, gsvs_itemsize,
 			   64, true, true, 4, 16, 0);
 
 	offset = gsvs_itemsize * 64;
-	si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS1,
+	si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
 			   sctx->gsvs_ring, gsvs_itemsize,
 			   64, true, true, 4, 16, offset);
 
 	offset = (gsvs_itemsize * 2) * 64;
-	si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS2,
+	si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
 			   sctx->gsvs_ring, gsvs_itemsize,
 			   64, true, true, 4, 16, offset);
 
 	offset = (gsvs_itemsize * 3) * 64;
-	si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_GS_RING_GSVS3,
+	si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
 			   sctx->gsvs_ring, gsvs_itemsize,
 			   64, true, true, 4, 16, offset);
 }
@@ -1792,9 +1792,8 @@ static void si_init_tess_factor_ring(struct si_context *sctx)
 	sctx->b.initial_gfx_cs_size = 0; /* force flush */
 	si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
 
-	si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_TESS_CTRL,
-			   SI_HS_RING_TESS_FACTOR, sctx->tf_ring, 0,
-			   sctx->tf_ring->width0, false, false, 0, 0, 0);
+	si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
+			   0, sctx->tf_ring->width0, false, false, 0, 0, 0);
 }
 
 /**