Mesa (master): anv: pipeline: gen7: fix assert in debug mode
Anuj Phogat
aphogat at kemper.freedesktop.org
Sat Aug 13 00:07:33 UTC 2016
Module: Mesa
Branch: master
Commit: 0294dd00ccdab2c20d5df786ba780d7e091c2ab4
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0294dd00ccdab2c20d5df786ba780d7e091c2ab4
Author: Lionel Landwerlin <llandwerlin at gmail.com>
Date: Thu Aug 11 18:25:09 2016 +0100
anv: pipeline: gen7: fix assert in debug mode
SampleMask is only 8bits long on gen7.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97278
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.phogat at gmail.com>
---
src/intel/vulkan/genX_pipeline_util.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/intel/vulkan/genX_pipeline_util.h b/src/intel/vulkan/genX_pipeline_util.h
index cf2adb0..679fb57 100644
--- a/src/intel/vulkan/genX_pipeline_util.h
+++ b/src/intel/vulkan/genX_pipeline_util.h
@@ -463,7 +463,11 @@ emit_ms_state(struct anv_pipeline *pipeline,
*
* 3DSTATE_SAMPLE_MASK.SampleMask is 16 bits.
*/
+#if GEN_GEN >= 8
uint32_t sample_mask = 0xffff;
+#else
+ uint32_t sample_mask = 0xff;
+#endif
if (info) {
samples = info->rasterizationSamples;
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