Mesa (master): i965/fs: Lower TEX to TXL during NIR translation.

[Francisco Jerez]

Module: Mesa
Branch: master
Commit: 0c754d1c4203d87dbb9d2dd882ef42686e6d01ec
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c754d1c4203d87dbb9d2dd882ef42686e6d01ec

Author: Francisco Jerez <currojerez at riseup.net>
Date:   Fri Aug 12 11:38:29 2016 -0700

i965/fs: Lower TEX to TXL during NIR translation.

This simplifies the code slightly and will allow the SIMD lowering
pass to find out easily what the actual texturing opcode is in order
to determine the maximum execution size of texturing instructions.

Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>

---

 src/mesa/drivers/dri/i965/brw_fs.cpp     | 10 ----------
 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 10 ++++++----
 2 files changed, 6 insertions(+), 14 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d1ac80a..f236089 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -4091,16 +4091,6 @@ lower_sampler_logical_send_gen7(const fs_builder &bld, fs_inst *inst, opcode op,
 
    bool coordinate_done = false;
 
-   /* The sampler can only meaningfully compute LOD for fragment shader
-    * messages. For all other stages, we change the opcode to TXL and
-    * hardcode the LOD to 0.
-    */
-   if (bld.shader->stage != MESA_SHADER_FRAGMENT &&
-       op == SHADER_OPCODE_TEX) {
-      op = SHADER_OPCODE_TXL;
-      lod = brw_imm_f(0.0f);
-   }
-
    /* Set up the LOD info */
    switch (op) {
    case FS_OPCODE_TXB:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 134cd01..df033e1 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -4439,9 +4439,10 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
    srcs[TEX_LOGICAL_SRC_COORD_COMPONENTS] = brw_imm_d(instr->coord_components);
    srcs[TEX_LOGICAL_SRC_GRAD_COMPONENTS] = brw_imm_d(lod_components);
 
-   if (instr->op == nir_texop_query_levels) {
-      /* textureQueryLevels() is implemented in terms of TXS so we need to
-       * pass a valid LOD argument.
+   if (instr->op == nir_texop_query_levels ||
+       (instr->op == nir_texop_tex && stage != MESA_SHADER_FRAGMENT)) {
+      /* textureQueryLevels() and texture() are implemented in terms of TXS
+       * and TXL respectively, so we need to pass a valid LOD argument.
        */
       assert(srcs[TEX_LOGICAL_SRC_LOD].file == BAD_FILE);
       srcs[TEX_LOGICAL_SRC_LOD] = brw_imm_ud(0u);
@@ -4450,7 +4451,8 @@ fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
    enum opcode opcode;
    switch (instr->op) {
    case nir_texop_tex:
-      opcode = SHADER_OPCODE_TEX_LOGICAL;
+      opcode = (stage == MESA_SHADER_FRAGMENT ? SHADER_OPCODE_TEX_LOGICAL :
+                SHADER_OPCODE_TXL_LOGICAL);
       break;
    case nir_texop_txb:
       opcode = FS_OPCODE_TXB_LOGICAL;