Mesa (master): ttn: Make FRAG_RESULT_DEPTH be a float variable to match gtn and ptn.

[Eric Anholt]

Module: Mesa
Branch: master
Commit: ed92241d7848a5f08360240795869d72b68054a3
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed92241d7848a5f08360240795869d72b68054a3

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Jul 26 16:19:15 2016 -0700

ttn: Make FRAG_RESULT_DEPTH be a float variable to match gtn and ptn.

This lets TTN-using drivers handle FRAG_RESULT_DEPTH the same between all
their source paths.

Reviewed-by: Rob Clark <robdclark at gmail.com>

---

 src/gallium/auxiliary/nir/tgsi_to_nir.c              | 19 ++++++++++++++++---
 src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c |  6 ------
 src/gallium/drivers/freedreno/ir3/ir3_shader.c       |  1 -
 src/gallium/drivers/vc4/vc4_program.c                |  2 +-
 4 files changed, 17 insertions(+), 11 deletions(-)

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 65eca6f..3d80ef0 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -1918,9 +1918,22 @@ ttn_add_output_stores(struct ttn_compile *c)
          nir_intrinsic_instr *store =
             nir_intrinsic_instr_create(b->shader, nir_intrinsic_store_output);
          unsigned loc = var->data.driver_location + i;
-         store->num_components = 4;
-         store->src[0].reg.reg = c->output_regs[loc].reg;
-         store->src[0].reg.base_offset = c->output_regs[loc].offset;
+
+         nir_src src = nir_src_for_reg(c->output_regs[loc].reg);
+         src.reg.base_offset = c->output_regs[loc].offset;
+
+         if (c->build.shader->stage == MESA_SHADER_FRAGMENT &&
+             var->data.location == FRAG_RESULT_DEPTH) {
+            /* TGSI uses TGSI_SEMANTIC_POSITION.z for the depth output, while
+             * NIR uses a single float FRAG_RESULT_DEPTH.
+             */
+            src = nir_src_for_ssa(nir_channel(b, nir_ssa_for_src(b, src, 4), 2));
+            store->num_components = 1;
+         } else {
+            store->num_components = 4;
+         }
+         store->src[0] = src;
+
          nir_intrinsic_set_base(store, loc);
          nir_intrinsic_set_write_mask(store, 0xf);
          store->src[1] = nir_src_for_ssa(nir_imm_int(b, 0));
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
index 2331901..6323566 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c
@@ -2498,12 +2498,6 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
 	/* fixup input/outputs: */
 	for (i = 0; i < so->outputs_count; i++) {
 		so->outputs[i].regid = ir->outputs[i*4]->regs[0]->num;
-		/* preserve hack for depth output.. tgsi writes depth to .z,
-		 * but what we give the hw is the scalar register:
-		 */
-		if (so->shader->from_tgsi && (so->type == SHADER_FRAGMENT) &&
-				(so->outputs[i].slot == FRAG_RESULT_DEPTH))
-			so->outputs[i].regid += 2;
 	}
 
 	/* Note that some or all channels of an input may be unused: */
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.c b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
index 87bdcf9..ac48132 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.c
@@ -294,7 +294,6 @@ ir3_shader_create(struct ir3_compiler *compiler,
 			tgsi_dump(cso->tokens, 0);
 		}
 		nir = ir3_tgsi_to_nir(cso->tokens);
-		shader->from_tgsi = true;
 	}
 	/* do first pass optimization, ignoring the key: */
 	shader->nir = ir3_optimize_nir(shader, nir, NULL);
diff --git a/src/gallium/drivers/vc4/vc4_program.c b/src/gallium/drivers/vc4/vc4_program.c
index 030643a..33721f1 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1223,7 +1223,7 @@ emit_frag_end(struct vc4_compile *c)
                 if (c->output_position_index != -1) {
                         qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
                                       qir_FMUL(c,
-                                               c->outputs[c->output_position_index + 2],
+                                               c->outputs[c->output_position_index],
                                                qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
                 } else {
                         qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),