Mesa (master): i965: Track that the stencil data was updated when clearing

[Jordan Justen]

Module: Mesa
Branch: master
Commit: 7bd87c1e6e168b048cdf2318af8848d07caa6706
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bd87c1e6e168b048cdf2318af8848d07caa6706

Author: Jordan Justen <jordan.l.justen at intel.com>
Date:   Sat Jun 11 16:27:48 2016 -0700

i965: Track that the stencil data was updated when clearing

Signed-off-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick at intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen at intel.com>

---

 src/mesa/drivers/dri/i965/brw_clear.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 1dfff09..18b8fcb 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -239,6 +239,14 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
       }
    }
 
+   if (mask & BUFFER_BIT_STENCIL) {
+      struct intel_renderbuffer *stencil_irb =
+         intel_get_renderbuffer(fb, BUFFER_STENCIL);
+      struct intel_mipmap_tree *mt = stencil_irb->mt;
+      if (mt && mt->stencil_mt)
+         mt->stencil_mt->r8stencil_needs_update = true;
+   }
+
    /* BLORP is currently only supported on Gen6+. */
    if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) {
       const bool encode_srgb = ctx->Color.sRGBEnabled;