Mesa (master): freedreno/a5xx: fix draw packet size with index buffer

[Rob Clark]

Module: Mesa
Branch: master
Commit: a9383ae6d6eb71d30433b0346367af63bc979d34
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9383ae6d6eb71d30433b0346367af63bc979d34

Author: Rob Clark <robdclark at gmail.com>
Date:   Tue Dec  6 15:52:28 2016 -0500

freedreno/a5xx: fix draw packet size with index buffer

gpuaddr of idx buffer is now two dwords (64b).

Signed-off-by: Rob Clark <robdclark at gmail.com>

---

 src/gallium/drivers/freedreno/a5xx/fd5_draw.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h
index 677bedf..8ce70d3 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_draw.h
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_draw.h
@@ -53,7 +53,7 @@ fd5_draw(struct fd_batch *batch, struct fd_ringbuffer *ring,
 	 */
 	emit_marker5(ring, 7);
 
-	OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 6 : 3);
+	OUT_PKT7(ring, CP_DRAW_INDX_OFFSET, idx_buffer ? 7 : 3);
 	if (vismode == USE_VISIBILITY) {
 		/* leave vis mode blank for now, it will be patched up when
 		 * we know if we are binning or not