Mesa (master): radv: consolidate compute pipeline flushing (v1.1)

[Dave Airlie]

Module: Mesa
Branch: master
Commit: eb2ba5c8df2149f92298e090508f1193026811a9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb2ba5c8df2149f92298e090508f1193026811a9

Author: Dave Airlie <airlied at redhat.com>
Date:   Mon Nov 28 00:32:22 2016 +0000

radv: consolidate compute pipeline flushing (v1.1)

This just moves some common code into a utility function
to avoid having to change multiple places later.

v1.1: rename function to better reflect what it does. (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied at redhat.com>

---

 src/amd/vulkan/radv_cmd_buffer.c | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index ddffa27..ea5b62e 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2001,6 +2001,15 @@ void radv_CmdDrawIndexedIndirectCountAMD(
 	                                     maxDrawCount, stride);
 }
 
+static void
+radv_flush_compute_state(struct radv_cmd_buffer *cmd_buffer)
+{
+	radv_emit_compute_pipeline(cmd_buffer);
+	radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline->layout,
+			     VK_SHADER_STAGE_COMPUTE_BIT);
+	si_emit_cache_flush(cmd_buffer);
+}
+
 void radv_CmdDispatch(
 	VkCommandBuffer                             commandBuffer,
 	uint32_t                                    x,
@@ -2009,10 +2018,8 @@ void radv_CmdDispatch(
 {
 	RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
-	radv_emit_compute_pipeline(cmd_buffer);
-	radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline->layout,
-			     VK_SHADER_STAGE_COMPUTE_BIT);
-	si_emit_cache_flush(cmd_buffer);
+	radv_flush_compute_state(cmd_buffer);
+
 	unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 10);
 
 	radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + AC_USERDATA_CS_GRID_SIZE * 4, 3);
@@ -2042,10 +2049,7 @@ void radv_CmdDispatchIndirect(
 
 	cmd_buffer->device->ws->cs_add_buffer(cmd_buffer->cs, buffer->bo, 8);
 
-	radv_emit_compute_pipeline(cmd_buffer);
-	radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline->layout,
-			     VK_SHADER_STAGE_COMPUTE_BIT);
-	si_emit_cache_flush(cmd_buffer);
+	radv_flush_compute_state(cmd_buffer);
 
 	unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 25);
 
@@ -2092,10 +2096,8 @@ void radv_unaligned_dispatch(
 	remainder[1] = y + compute_shader->info.cs.block_size[1] - align_u32_npot(y, compute_shader->info.cs.block_size[1]);
 	remainder[2] = z + compute_shader->info.cs.block_size[2] - align_u32_npot(z, compute_shader->info.cs.block_size[2]);
 
-	radv_emit_compute_pipeline(cmd_buffer);
-	radv_flush_constants(cmd_buffer, cmd_buffer->state.compute_pipeline->layout,
-			     VK_SHADER_STAGE_COMPUTE_BIT);
-	si_emit_cache_flush(cmd_buffer);
+	radv_flush_compute_state(cmd_buffer);
+
 	unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 15);
 
 	radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);